Patents by Inventor Chien Sen Weng

Chien Sen Weng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12114547
    Abstract: Provided is a display panel, including a substrate, multiple pixel circuits, an insulating layer, multiple first electrodes, a first isolation structure, and a second isolation structure. The pixel circuits are located on the substrate. The insulating layer is located on the pixel circuits and has multiple through holes. The first electrodes are located on the insulating layer and are respectively electrically connected to the pixel circuits through the through holes. The first isolation structure is located on the insulating layer and overlaps the through holes. The second isolation structure includes multiple separating parts and multiple cover parts. The separating parts and the first isolation structure at least partially overlap, and the cover parts respectively overlap the through holes and the first isolation structure.
    Type: Grant
    Filed: November 5, 2021
    Date of Patent: October 8, 2024
    Assignee: Au Optronics Corporation
    Inventors: Kuo-Jui Chang, Wen-Tai Chen, Chi-Sheng Chiang, Yu-Chuan Liao, Chien-Sen Weng, Ming-Wei Sun
  • Publication number: 20240234535
    Abstract: A thin film transistor includes a substrate, a semiconductor layer, a gate insulating layer, a gate, a source and a drain. The semiconductor layer is located above the substrate. The gate insulating layer is located above the semiconductor layer. The gate is located above the gate insulating layer and overlapping with the semiconductor layer. The gate includes a first portion, a second portion and a third portion. The first portion is extending along the surface of the gate insulating layer and directly in contact with the gate insulating layer. The second portion is separated from the gate insulating layer. Taking the surface of the gate insulating layer as a reference, the top surface of the second portion is higher than the top surface of the first portion. The third portion connects the first portion to the second portion. The source and the drain are electrically connected to the semiconductor layer.
    Type: Application
    Filed: December 1, 2022
    Publication date: July 11, 2024
    Applicant: AUO Corporation
    Inventors: Kuo-Jui Chang, Wen-Tai Chen, Chi-Sheng Chiang, Yu-Chuan Liao, Chien-Sen Weng, Ming-Wei Sun
  • Publication number: 20240136420
    Abstract: A thin film transistor includes a substrate, a semiconductor layer, a gate insulating layer, a gate, a source and a drain. The semiconductor layer is located above the substrate. The gate insulating layer is located above the semiconductor layer. The gate is located above the gate insulating layer and overlapping with the semiconductor layer. The gate includes a first portion, a second portion and a third portion. The first portion is extending along the surface of the gate insulating layer and directly in contact with the gate insulating layer. The second portion is separated from the gate insulating layer. Taking the surface of the gate insulating layer as a reference, the top surface of the second portion is higher than the top surface of the first portion. The third portion connects the first portion to the second portion. The source and the drain are electrically connected to the semiconductor layer.
    Type: Application
    Filed: December 1, 2022
    Publication date: April 25, 2024
    Applicant: AUO Corporation
    Inventors: Kuo-Jui Chang, Wen-Tai Chen, Chi-Sheng Chiang, Yu-Chuan Liao, Chien-Sen Weng, Ming-Wei Sun
  • Patent number: 11778867
    Abstract: A display panel includes a substrate, a first isolation structure, a second isolation structure and a plurality of light emitting structures. The first isolation structure is disposed on the substrate and includes a plurality of through holes. The second isolation substrate is laminated on the first isolation substrate and fills up the plurality of through holes of the first isolation substrate. The plurality of light emitting structures are disposed on the substrate and are isolated from each other via the second isolation structure.
    Type: Grant
    Filed: July 26, 2021
    Date of Patent: October 3, 2023
    Assignee: Au Optronics Corporation
    Inventors: Kuo-Jui Chang, Wen-Tai Chen, Chi-Sheng Chiang, Chien-Sen Weng, Ming-Wei Sun
  • Publication number: 20220367591
    Abstract: Provided is a display panel, including a substrate, multiple pixel circuits, an insulating layer, multiple first electrodes, a first isolation structure, and a second isolation structure. The pixel circuits are located on the substrate. The insulating layer is located on the pixel circuits and has multiple through holes. The first electrodes are located on the insulating layer and are respectively electrically connected to the pixel circuits through the through holes. The first isolation structure is located on the insulating layer and overlaps the through holes. The second isolation structure includes multiple separating parts and multiple cover parts. The separating parts and the first isolation structure at least partially overlap, and the cover parts respectively overlap the through holes and the first isolation structure.
    Type: Application
    Filed: November 5, 2021
    Publication date: November 17, 2022
    Applicant: Au Optronics Corporation
    Inventors: Kuo-Jui Chang, Wen-Tai Chen, Chi-Sheng Chiang, Yu-Chuan Liao, Chien-Sen Weng, Ming-Wei Sun
  • Patent number: 11450719
    Abstract: An organic light-emitting panel, including a substrate, a planarization layer, a reflective layer and a bank layer, is provided. The substrate has a display region and a periphery region beside the display region. The planarization layer is disposed on the substrate and has an indentation. The reflective layer is disposed on the planarization layer. The reflective layer is formed along a sidewall of the indentation. The bank layer is disposed on the planarization layer, covers the indentation, and has a periphery taper surface. The indentation is adjacent to the periphery taper surface and is closer to the display region than the periphery taper surface. A fabrication method of the above organic light-emitting panel is also provided.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: September 20, 2022
    Assignee: Au Optronics Corporation
    Inventors: Kuo-Jui Chang, Chien-Sen Weng, Ming-Wei Sun
  • Publication number: 20220262875
    Abstract: A display panel includes a substrate, a first isolation structure, a second isolation structure and a plurality of light emitting structures. The first isolation structure is disposed on the substrate and includes a plurality of through holes. The second isolation substrate is laminated on the first isolation substrate and fills up the plurality of through holes of the first isolation substrate. The plurality of light emitting structures are disposed on the substrate and are isolated from each other via the second isolation structure.
    Type: Application
    Filed: July 26, 2021
    Publication date: August 18, 2022
    Applicant: Au Optronics Corporation
    Inventors: Kuo-Jui Chang, Wen-Tai Chen, Chi-Sheng Chiang, Chien-Sen Weng, Ming-Wei Sun
  • Publication number: 20210399066
    Abstract: An organic light-emitting panel, including a substrate, a planarization layer, a reflective layer and a bank layer, is provided. The substrate has a display region and a periphery region beside the display region. The planarization layer is disposed on the substrate and has an indentation. The reflective layer is disposed on the planarization layer. The reflective layer is formed along a sidewall of the indentation. The bank layer is disposed on the planarization layer, covers the indentation, and has a periphery taper surface. The indentation is adjacent to the periphery taper surface and is closer to the display region than the periphery taper surface. A fabrication method of the above organic light-emitting panel is also provided.
    Type: Application
    Filed: September 15, 2020
    Publication date: December 23, 2021
    Applicant: Au Optronics Corporation
    Inventors: Kuo-Jui Chang, Chien-Sen Weng, Ming-Wei Sun
  • Publication number: 20180024513
    Abstract: In a data management system, a host is configured to send a data access request to a target measurement device among a plurality of measurement devices using a USB dongle. When the USB dongle is unable to receive data from the target measurement device within a predetermined period of time, the host determines that a connection interruption has occurred and releases the connection resource of the USB dongle.
    Type: Application
    Filed: June 21, 2017
    Publication date: January 25, 2018
    Inventors: Hao-Chun Tung, Chen-Chen Tsai, Chien-Sen Weng, Yung-Ti Wang
  • Patent number: 8415182
    Abstract: A manufacturing method of a thin film transistor array substrate is provided. In the method, a substrate having a display region and a sensing region is provided. At least a display thin film transistor is formed in the display region, a first sensing electrode is formed in the sensing region, and an inter-layer dielectric layer is disposed on the substrate, covers the display thin film transistor, and exposes the first sensing electrode. A patterned photo sensitive dielectric layer is then formed on the first sensing electrode. A patterned transparent conductive layer is subsequently formed on the substrate, wherein the patterned transparent conductive layer includes a pixel electrode coupled to the corresponding display thin film transistor and includes a second sensing electrode located on the patterned photo sensitive dielectric layer. A manufacturing method of a liquid crystal display panel adopting the aforementioned thin film transistor array substrate is also provided.
    Type: Grant
    Filed: December 22, 2009
    Date of Patent: April 9, 2013
    Assignee: Au Optronics Corporation
    Inventors: An-Thung Cho, Chia-Tien Peng, Yuan-Jun Hsu, Ching-Chieh Shih, Chien-Sen Weng, Kun-Chih Lin, Hang-Wei Tseug, Ming-Huang Chuang
  • Patent number: 8373179
    Abstract: A LED chip including a substrate, a semiconductor device layer, a current blocking layer, a current spread layer, a first electrode and a second electrode is provided. The semiconductor device layer is disposed on the substrate. The current blocking layer is disposed on a part of the semiconductor device layer and includes a current blocking segment and a current distribution adjusting segment. The current spread layer is disposed on a part of the semiconductor device layer and covers the current blocking layer. The first electrode is disposed on the current spread layer, wherein a part of the current blocking segment is overlapped with the first electrode. Contours of the current blocking segment and the first electrode are similar figures. Contour of the first electrode and is within contour of the current blocking segment. The current distribution adjusting segment is not overlapped with the first electrode.
    Type: Grant
    Filed: June 14, 2011
    Date of Patent: February 12, 2013
    Assignee: Lextar Electronics Corp.
    Inventors: Kuo-Lung Fang, Chien-Sen Weng, Chih-Wei Chao
  • Publication number: 20130029476
    Abstract: A dicing process is provided for cutting a wafer along a plurality of predetermined scribe lines into a plurality of dies that are releasably adhered to a release film. The dicing process includes: (a) disposing a wafer-breaking carrier on a supporting device, the wafer-breaking carrier having a chipping unit; (b) disposing the wafer above the supporting device such that the chipping unit is at a position corresponding to the scribe lines; and (c) adhering a release surface of the release film to the wafer by applying a force to the release film to contact the chipping unit of the wafer-breaking carrier with the wafer, such that the wafer is split along the scribe lines into the dies.
    Type: Application
    Filed: July 3, 2012
    Publication date: January 31, 2013
    Applicant: LEXTAR ELECTRONICS CORP.
    Inventors: Chien-Sen WENG, Mong-Yeng Xing, Yu-Ching Chang, Wei-Chang Yu, Yao-Hui Lin
  • Patent number: 8329487
    Abstract: In a fabricating method of an LED, a first-type doped semiconductor material layer, a light emitting material layer, and a second-type doped semiconductor material layer are sequentially formed on a substrate. The first-type and second-type doped semiconductor material layers and the light emitting material layer are patterned to form a first-type doped semiconductor layer, an active layer, and a second-type doped semiconductor layer. The active layer is disposed on a portion of the first-type doped semiconductor layer. The second-type doped semiconductor layer is disposed on the active layer and has a first top surface. A wall structure is formed on the first-type doped semiconductor layer that is not covered by the active layer, and the wall structure surrounds the active layer and has a second top surface higher than the first top surface of the second-type doped semiconductor layer. Electrodes are formed on the first-type and second-type doped semiconductor layers.
    Type: Grant
    Filed: November 1, 2010
    Date of Patent: December 11, 2012
    Assignee: Lextar Electronics Corp.
    Inventors: Kuo-Lung Fang, Chien-Sen Weng, Chih-Wei Chao
  • Patent number: 8314898
    Abstract: A display device includes a first substrate, a heating layer formed on the first substrate, an insulating layer having a first opening formed on the heating layer, at least one switching device, two contact pads formed on the insulating layer, and respectively electrically connected to the scan line and the data line, a capacitor, a passivation layer covering the switching device and the capacitor, and a pixel electrode formed on the passivation layer and electrically connected to the drain of the switching device. The source of the switching device is connected to the data line. The passivation layer has a plurality of second openings exposing the contact pads.
    Type: Grant
    Filed: March 18, 2011
    Date of Patent: November 20, 2012
    Assignee: AU Optronics Corp.
    Inventors: Mao-Yi Chang, Chia-Tien Peng, Chih-Wei Chao, Chien-Sen Weng, Chao-Shun Liao
  • Patent number: 8283188
    Abstract: A method for fabricating a light emitting diode chip is provided. Firstly, a semiconductor device layer is formed on a substrate. Afterwards, a current spreading layer is formed on a portion of the semiconductor device layer. Then, a current blocking layer and a passivation layer are formed on a portion of the semiconductor device layer not covered by the current spreading layer. Finally, a first electrode is formed on the current blocking layer and the current spreading layer. Moreover, a second electrode is formed on the semiconductor device layer.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: October 9, 2012
    Assignee: Lextar Electronics Corp.
    Inventors: Kuo-Lung Fang, Chien-Sen Weng, Chih-Wei Chao
  • Patent number: 8232978
    Abstract: An optical reflective touch panel and pixels and a system thereof are provided. Each pixel of the optical reflective touch panel includes a display circuit and a sensing circuit. The display circuit controls the display of the pixel. The sensing circuit is coupled to the display circuit for sensing a sensitization state of the pixel during a turned-on period and a turned-off period of a backlight module and outputting a digital signal to notify an optical reflective touch panel system that whether the pixel is touched or not.
    Type: Grant
    Filed: May 14, 2009
    Date of Patent: July 31, 2012
    Assignee: Au Optronics Corporation
    Inventors: Wen-Jen Chiang, An-Thung Cho, Chrong-Jung Lin, Chia-Tien Peng, Ya-Chin King, Kun-Chih Lin, Chih-Wei Chao, Chien-Sen Weng, Feng-Yuan Gan
  • Publication number: 20120160227
    Abstract: A wafer splitting apparatus suitable for splitting a plurality of chip regions of a wafer into a plurality of independent dice is provided. The wafer splitting apparatus includes a splitting knife body and at least a vibrating hammer. The splitting knife body is disposed at one side of the wafer, and has a first surface facing the wafer. The first surface stretches over a plurality of chip regions in all extending directions of the first surface passing through a center of the first surface. The splitting knife body is disposed between the wafer and the vibrating hammer, and the vibrating hammer is suitable for knocking the splitting knife body in a direction toward the wafer to make the splitting knife body move toward the wafer, so as to split the chip regions of the wafer into a plurality of independent dice. A wafer splitting process is also provided.
    Type: Application
    Filed: March 9, 2011
    Publication date: June 28, 2012
    Applicant: LEXTAR ELECTRONICS CORP.
    Inventors: Chien-Sen Weng, Meng-Yeng Xing, Wei-Chang Yu, Chih-Sheng Chen, Yu-Ching Chang
  • Patent number: D1021955
    Type: Grant
    Filed: March 17, 2022
    Date of Patent: April 9, 2024
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Chia-Hui Chung, Chien-Sen Weng
  • Patent number: D1023056
    Type: Grant
    Filed: February 24, 2022
    Date of Patent: April 16, 2024
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Chia-Hui Chung, Chien-Sen Weng
  • Patent number: D1034692
    Type: Grant
    Filed: April 19, 2022
    Date of Patent: July 9, 2024
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Chia-Hui Chung, Chien-Sen Weng