Patents by Inventor Chien Sen Weng
Chien Sen Weng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12114547Abstract: Provided is a display panel, including a substrate, multiple pixel circuits, an insulating layer, multiple first electrodes, a first isolation structure, and a second isolation structure. The pixel circuits are located on the substrate. The insulating layer is located on the pixel circuits and has multiple through holes. The first electrodes are located on the insulating layer and are respectively electrically connected to the pixel circuits through the through holes. The first isolation structure is located on the insulating layer and overlaps the through holes. The second isolation structure includes multiple separating parts and multiple cover parts. The separating parts and the first isolation structure at least partially overlap, and the cover parts respectively overlap the through holes and the first isolation structure.Type: GrantFiled: November 5, 2021Date of Patent: October 8, 2024Assignee: Au Optronics CorporationInventors: Kuo-Jui Chang, Wen-Tai Chen, Chi-Sheng Chiang, Yu-Chuan Liao, Chien-Sen Weng, Ming-Wei Sun
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Publication number: 20240234535Abstract: A thin film transistor includes a substrate, a semiconductor layer, a gate insulating layer, a gate, a source and a drain. The semiconductor layer is located above the substrate. The gate insulating layer is located above the semiconductor layer. The gate is located above the gate insulating layer and overlapping with the semiconductor layer. The gate includes a first portion, a second portion and a third portion. The first portion is extending along the surface of the gate insulating layer and directly in contact with the gate insulating layer. The second portion is separated from the gate insulating layer. Taking the surface of the gate insulating layer as a reference, the top surface of the second portion is higher than the top surface of the first portion. The third portion connects the first portion to the second portion. The source and the drain are electrically connected to the semiconductor layer.Type: ApplicationFiled: December 1, 2022Publication date: July 11, 2024Applicant: AUO CorporationInventors: Kuo-Jui Chang, Wen-Tai Chen, Chi-Sheng Chiang, Yu-Chuan Liao, Chien-Sen Weng, Ming-Wei Sun
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Publication number: 20240136420Abstract: A thin film transistor includes a substrate, a semiconductor layer, a gate insulating layer, a gate, a source and a drain. The semiconductor layer is located above the substrate. The gate insulating layer is located above the semiconductor layer. The gate is located above the gate insulating layer and overlapping with the semiconductor layer. The gate includes a first portion, a second portion and a third portion. The first portion is extending along the surface of the gate insulating layer and directly in contact with the gate insulating layer. The second portion is separated from the gate insulating layer. Taking the surface of the gate insulating layer as a reference, the top surface of the second portion is higher than the top surface of the first portion. The third portion connects the first portion to the second portion. The source and the drain are electrically connected to the semiconductor layer.Type: ApplicationFiled: December 1, 2022Publication date: April 25, 2024Applicant: AUO CorporationInventors: Kuo-Jui Chang, Wen-Tai Chen, Chi-Sheng Chiang, Yu-Chuan Liao, Chien-Sen Weng, Ming-Wei Sun
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Patent number: 11778867Abstract: A display panel includes a substrate, a first isolation structure, a second isolation structure and a plurality of light emitting structures. The first isolation structure is disposed on the substrate and includes a plurality of through holes. The second isolation substrate is laminated on the first isolation substrate and fills up the plurality of through holes of the first isolation substrate. The plurality of light emitting structures are disposed on the substrate and are isolated from each other via the second isolation structure.Type: GrantFiled: July 26, 2021Date of Patent: October 3, 2023Assignee: Au Optronics CorporationInventors: Kuo-Jui Chang, Wen-Tai Chen, Chi-Sheng Chiang, Chien-Sen Weng, Ming-Wei Sun
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Publication number: 20220367591Abstract: Provided is a display panel, including a substrate, multiple pixel circuits, an insulating layer, multiple first electrodes, a first isolation structure, and a second isolation structure. The pixel circuits are located on the substrate. The insulating layer is located on the pixel circuits and has multiple through holes. The first electrodes are located on the insulating layer and are respectively electrically connected to the pixel circuits through the through holes. The first isolation structure is located on the insulating layer and overlaps the through holes. The second isolation structure includes multiple separating parts and multiple cover parts. The separating parts and the first isolation structure at least partially overlap, and the cover parts respectively overlap the through holes and the first isolation structure.Type: ApplicationFiled: November 5, 2021Publication date: November 17, 2022Applicant: Au Optronics CorporationInventors: Kuo-Jui Chang, Wen-Tai Chen, Chi-Sheng Chiang, Yu-Chuan Liao, Chien-Sen Weng, Ming-Wei Sun
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Patent number: 11450719Abstract: An organic light-emitting panel, including a substrate, a planarization layer, a reflective layer and a bank layer, is provided. The substrate has a display region and a periphery region beside the display region. The planarization layer is disposed on the substrate and has an indentation. The reflective layer is disposed on the planarization layer. The reflective layer is formed along a sidewall of the indentation. The bank layer is disposed on the planarization layer, covers the indentation, and has a periphery taper surface. The indentation is adjacent to the periphery taper surface and is closer to the display region than the periphery taper surface. A fabrication method of the above organic light-emitting panel is also provided.Type: GrantFiled: September 15, 2020Date of Patent: September 20, 2022Assignee: Au Optronics CorporationInventors: Kuo-Jui Chang, Chien-Sen Weng, Ming-Wei Sun
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Publication number: 20220262875Abstract: A display panel includes a substrate, a first isolation structure, a second isolation structure and a plurality of light emitting structures. The first isolation structure is disposed on the substrate and includes a plurality of through holes. The second isolation substrate is laminated on the first isolation substrate and fills up the plurality of through holes of the first isolation substrate. The plurality of light emitting structures are disposed on the substrate and are isolated from each other via the second isolation structure.Type: ApplicationFiled: July 26, 2021Publication date: August 18, 2022Applicant: Au Optronics CorporationInventors: Kuo-Jui Chang, Wen-Tai Chen, Chi-Sheng Chiang, Chien-Sen Weng, Ming-Wei Sun
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Publication number: 20210399066Abstract: An organic light-emitting panel, including a substrate, a planarization layer, a reflective layer and a bank layer, is provided. The substrate has a display region and a periphery region beside the display region. The planarization layer is disposed on the substrate and has an indentation. The reflective layer is disposed on the planarization layer. The reflective layer is formed along a sidewall of the indentation. The bank layer is disposed on the planarization layer, covers the indentation, and has a periphery taper surface. The indentation is adjacent to the periphery taper surface and is closer to the display region than the periphery taper surface. A fabrication method of the above organic light-emitting panel is also provided.Type: ApplicationFiled: September 15, 2020Publication date: December 23, 2021Applicant: Au Optronics CorporationInventors: Kuo-Jui Chang, Chien-Sen Weng, Ming-Wei Sun
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Publication number: 20180024513Abstract: In a data management system, a host is configured to send a data access request to a target measurement device among a plurality of measurement devices using a USB dongle. When the USB dongle is unable to receive data from the target measurement device within a predetermined period of time, the host determines that a connection interruption has occurred and releases the connection resource of the USB dongle.Type: ApplicationFiled: June 21, 2017Publication date: January 25, 2018Inventors: Hao-Chun Tung, Chen-Chen Tsai, Chien-Sen Weng, Yung-Ti Wang
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Patent number: 8415182Abstract: A manufacturing method of a thin film transistor array substrate is provided. In the method, a substrate having a display region and a sensing region is provided. At least a display thin film transistor is formed in the display region, a first sensing electrode is formed in the sensing region, and an inter-layer dielectric layer is disposed on the substrate, covers the display thin film transistor, and exposes the first sensing electrode. A patterned photo sensitive dielectric layer is then formed on the first sensing electrode. A patterned transparent conductive layer is subsequently formed on the substrate, wherein the patterned transparent conductive layer includes a pixel electrode coupled to the corresponding display thin film transistor and includes a second sensing electrode located on the patterned photo sensitive dielectric layer. A manufacturing method of a liquid crystal display panel adopting the aforementioned thin film transistor array substrate is also provided.Type: GrantFiled: December 22, 2009Date of Patent: April 9, 2013Assignee: Au Optronics CorporationInventors: An-Thung Cho, Chia-Tien Peng, Yuan-Jun Hsu, Ching-Chieh Shih, Chien-Sen Weng, Kun-Chih Lin, Hang-Wei Tseug, Ming-Huang Chuang
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Patent number: 8373179Abstract: A LED chip including a substrate, a semiconductor device layer, a current blocking layer, a current spread layer, a first electrode and a second electrode is provided. The semiconductor device layer is disposed on the substrate. The current blocking layer is disposed on a part of the semiconductor device layer and includes a current blocking segment and a current distribution adjusting segment. The current spread layer is disposed on a part of the semiconductor device layer and covers the current blocking layer. The first electrode is disposed on the current spread layer, wherein a part of the current blocking segment is overlapped with the first electrode. Contours of the current blocking segment and the first electrode are similar figures. Contour of the first electrode and is within contour of the current blocking segment. The current distribution adjusting segment is not overlapped with the first electrode.Type: GrantFiled: June 14, 2011Date of Patent: February 12, 2013Assignee: Lextar Electronics Corp.Inventors: Kuo-Lung Fang, Chien-Sen Weng, Chih-Wei Chao
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Publication number: 20130029476Abstract: A dicing process is provided for cutting a wafer along a plurality of predetermined scribe lines into a plurality of dies that are releasably adhered to a release film. The dicing process includes: (a) disposing a wafer-breaking carrier on a supporting device, the wafer-breaking carrier having a chipping unit; (b) disposing the wafer above the supporting device such that the chipping unit is at a position corresponding to the scribe lines; and (c) adhering a release surface of the release film to the wafer by applying a force to the release film to contact the chipping unit of the wafer-breaking carrier with the wafer, such that the wafer is split along the scribe lines into the dies.Type: ApplicationFiled: July 3, 2012Publication date: January 31, 2013Applicant: LEXTAR ELECTRONICS CORP.Inventors: Chien-Sen WENG, Mong-Yeng Xing, Yu-Ching Chang, Wei-Chang Yu, Yao-Hui Lin
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Patent number: 8329487Abstract: In a fabricating method of an LED, a first-type doped semiconductor material layer, a light emitting material layer, and a second-type doped semiconductor material layer are sequentially formed on a substrate. The first-type and second-type doped semiconductor material layers and the light emitting material layer are patterned to form a first-type doped semiconductor layer, an active layer, and a second-type doped semiconductor layer. The active layer is disposed on a portion of the first-type doped semiconductor layer. The second-type doped semiconductor layer is disposed on the active layer and has a first top surface. A wall structure is formed on the first-type doped semiconductor layer that is not covered by the active layer, and the wall structure surrounds the active layer and has a second top surface higher than the first top surface of the second-type doped semiconductor layer. Electrodes are formed on the first-type and second-type doped semiconductor layers.Type: GrantFiled: November 1, 2010Date of Patent: December 11, 2012Assignee: Lextar Electronics Corp.Inventors: Kuo-Lung Fang, Chien-Sen Weng, Chih-Wei Chao
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Patent number: 8314898Abstract: A display device includes a first substrate, a heating layer formed on the first substrate, an insulating layer having a first opening formed on the heating layer, at least one switching device, two contact pads formed on the insulating layer, and respectively electrically connected to the scan line and the data line, a capacitor, a passivation layer covering the switching device and the capacitor, and a pixel electrode formed on the passivation layer and electrically connected to the drain of the switching device. The source of the switching device is connected to the data line. The passivation layer has a plurality of second openings exposing the contact pads.Type: GrantFiled: March 18, 2011Date of Patent: November 20, 2012Assignee: AU Optronics Corp.Inventors: Mao-Yi Chang, Chia-Tien Peng, Chih-Wei Chao, Chien-Sen Weng, Chao-Shun Liao
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Patent number: 8283188Abstract: A method for fabricating a light emitting diode chip is provided. Firstly, a semiconductor device layer is formed on a substrate. Afterwards, a current spreading layer is formed on a portion of the semiconductor device layer. Then, a current blocking layer and a passivation layer are formed on a portion of the semiconductor device layer not covered by the current spreading layer. Finally, a first electrode is formed on the current blocking layer and the current spreading layer. Moreover, a second electrode is formed on the semiconductor device layer.Type: GrantFiled: August 30, 2011Date of Patent: October 9, 2012Assignee: Lextar Electronics Corp.Inventors: Kuo-Lung Fang, Chien-Sen Weng, Chih-Wei Chao
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Patent number: 8232978Abstract: An optical reflective touch panel and pixels and a system thereof are provided. Each pixel of the optical reflective touch panel includes a display circuit and a sensing circuit. The display circuit controls the display of the pixel. The sensing circuit is coupled to the display circuit for sensing a sensitization state of the pixel during a turned-on period and a turned-off period of a backlight module and outputting a digital signal to notify an optical reflective touch panel system that whether the pixel is touched or not.Type: GrantFiled: May 14, 2009Date of Patent: July 31, 2012Assignee: Au Optronics CorporationInventors: Wen-Jen Chiang, An-Thung Cho, Chrong-Jung Lin, Chia-Tien Peng, Ya-Chin King, Kun-Chih Lin, Chih-Wei Chao, Chien-Sen Weng, Feng-Yuan Gan
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Publication number: 20120160227Abstract: A wafer splitting apparatus suitable for splitting a plurality of chip regions of a wafer into a plurality of independent dice is provided. The wafer splitting apparatus includes a splitting knife body and at least a vibrating hammer. The splitting knife body is disposed at one side of the wafer, and has a first surface facing the wafer. The first surface stretches over a plurality of chip regions in all extending directions of the first surface passing through a center of the first surface. The splitting knife body is disposed between the wafer and the vibrating hammer, and the vibrating hammer is suitable for knocking the splitting knife body in a direction toward the wafer to make the splitting knife body move toward the wafer, so as to split the chip regions of the wafer into a plurality of independent dice. A wafer splitting process is also provided.Type: ApplicationFiled: March 9, 2011Publication date: June 28, 2012Applicant: LEXTAR ELECTRONICS CORP.Inventors: Chien-Sen Weng, Meng-Yeng Xing, Wei-Chang Yu, Chih-Sheng Chen, Yu-Ching Chang
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Patent number: D1021955Type: GrantFiled: March 17, 2022Date of Patent: April 9, 2024Assignee: AU OPTRONICS CORPORATIONInventors: Chia-Hui Chung, Chien-Sen Weng
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Patent number: D1023056Type: GrantFiled: February 24, 2022Date of Patent: April 16, 2024Assignee: AU OPTRONICS CORPORATIONInventors: Chia-Hui Chung, Chien-Sen Weng
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Patent number: D1034692Type: GrantFiled: April 19, 2022Date of Patent: July 9, 2024Assignee: AU OPTRONICS CORPORATIONInventors: Chia-Hui Chung, Chien-Sen Weng