Patents by Inventor Chien-Wen LIN

Chien-Wen LIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210055764
    Abstract: An electronic device including two bodies and at least one hinge structure is provided. The hinge structure includes a first bracket, a second bracket, a first rotation component, and a second rotation component. The hinge structure is connected to the two bodies via the first bracket and the second bracket respectively. The first rotation component is connected rotatably to the first bracket by taking a first axis as a rotation axis. The second rotation component is connected rotatably to the first rotation component by taking the first axis as a rotation axis, and is connected rotatably to the second bracket by taking a second axis as a rotation axis, wherein the first axis and the second axis are parallel to each other.
    Type: Application
    Filed: August 19, 2020
    Publication date: February 25, 2021
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Cheng-Ya Chi, Chien-Chu Chen, Ken-Ping Lin, Cheng-Shiue Jan, Yao-Lin Chang, Han-Hsuan Tsai, Jui-Min Huang, Chih-Wen Chiang
  • Patent number: 10910268
    Abstract: A method of manufacturing chip package is disclosed. The method includes providing a wafer having a first surface and a second surface, in which the wafer includes conductive bumps disposed on the first surface; thinning the wafer from the second surface toward the first surface; dicing the wafer to form chips, in which each chip has a third surface and a fourth surface, and at least one of the conductive bumps is disposed on the third surface; disposing the chips on a substrate, such that the conductive bumps are disposed between the substrate and the third surface, in which any two adjacent of the chips are spaced apart by a gap ranging from 50 ?m to 140 ?m; forming an insulating layer filling the gaps and covering the chips; and dicing the insulating layer along each gap to form a plurality of chip packages.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: February 2, 2021
    Assignee: COMCHIP TECHNOLOGY CO., LTD.
    Inventors: Chien-Chih Lai, Hung-Wen Lin
  • Patent number: 10896639
    Abstract: A display apparatus with a border of reduced size includes pixel units arranged in a matrix. Each pixel unit includes a driving transistor. The display apparatus defines a display region and a non-display region. The display region includes horizontal scan lines and data lines. The horizontal scan lines are parallel with each along a first direction, and the data lines are parallel with each other along a second direction. A pixel group contains three pixels and these pixel units are arranged on different columns along the first direction, and in different rows along the second direction. The driving transistors of these pixel units are electrically connected to one data line through connection lines.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: January 19, 2021
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yu-Fu Weng, Chien-Wen Lin, Tzu-Yu Cheng
  • Publication number: 20200400153
    Abstract: A thermal module including a first body, a second body, a first fan assembly, a second fan assembly, and a shaft is provided. The first body and the second body are slidably connected to each other and form an accommodating space together. The first fan assembly is disposed in the accommodating space and has a first hub and a plurality of first fan blades. The first hub is connected to the first body. The second fan assembly is disposed in the accommodating space and has a second hub and a plurality of second fan blades, and the second hub is connected to the second body. The first hub and the second hub overlap each other. The shaft is pivotally disposed in the first body and the second body and is engaged with the first fan assembly and the second fan assembly.
    Type: Application
    Filed: October 8, 2019
    Publication date: December 24, 2020
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Jui-Min Huang, Chih-Wen Chiang, Chien-Chu Chen, Wei-Hao Lan, Ching-Ya Tu, Ken-Ping Lin
  • Publication number: 20200379323
    Abstract: A lens includes a casing, a first lens group, a second lens group and a heat dissipating member. The first lens group is disposed in the casing and close to a first side of the casing. The second lens group is disposed in the casing and close to a second side of the casing, wherein the first side is opposite to the second side. The heat dissipating member is disposed at the second side of the casing and contacts the casing.
    Type: Application
    Filed: April 26, 2020
    Publication date: December 3, 2020
    Inventors: Chien-Hung Lin, Tzu-Huan Hsu, Sheng-Wen Hu, Hsin-Jung Yeh, Chih-Chieh Tsung
  • Publication number: 20200355199
    Abstract: A fan module including a body and a plurality of blades is provided. The body has a rotating axis and the body is telescopic along the rotating axis to have an elongated state and a shortened state. The blades are respectively disposed on the body and rotate along with the body along the rotating axis. At least a portion of each blade is flexible and a bending state of each blade is changed along with the elongated state or the shortened state of the body. An axial size of each blade along the rotating axis when the body is in the elongated state is greater than the axial size of each blade along the rotating axis when the body is in the shortened state.
    Type: Application
    Filed: March 27, 2020
    Publication date: November 12, 2020
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Han-Hsuan Tsai, Jui-Min Huang, Wei-Hao Lan, Chien-Chu Chen, Ching-Ya Tu, Chih-Wen Chiang, Ching-Tai Chang, Ken-Ping Lin, Yao-Lin Chang, Cheng-Ya Chi
  • Publication number: 20200350404
    Abstract: Embodiments of mechanisms for forming dislocations in source and drain regions of finFET devices are provided. The mechanisms involve recessing fins and removing the dielectric material in the isolation structures neighboring fins to increase epitaxial regions for dislocation formation. The mechanisms also involve performing a pre-amorphous implantation (PAI) process either before or after the epitaxial growth in the recessed source and drain regions. An anneal process after the PAI process enables consistent growth of the dislocations in the source and drain regions. The dislocations in the source and drain regions (or stressor regions) can form consistently to produce targeted strain in the source and drain regions to improve carrier mobility and device performance for NMOS devices.
    Type: Application
    Filed: July 20, 2020
    Publication date: November 5, 2020
    Inventors: Chun Hsiung Tsai, Wei-Yuan Lu, Chien-Tai Chan, Wei-Yang Lee, Da-Wen Lin
  • Patent number: 10816891
    Abstract: A method of manufacturing a mask includes depositing an end-point layer over a light transmitting substrate, depositing a phase shifter over the end-point layer, depositing a hard mask layer over the phase shifter, and removing a portion of the hard mask layer and a first portion of the phase shifter to expose a portion of the end-point layer. The end-point layer and the light transmitting substrate are transparent to a predetermined wavelength.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: October 27, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hao-Ming Chang, Chien-Hung Lai, Cheng-Ming Lin, Hsuan-Wen Wang, Min-An Yang, S. C. Hsu, Shao-Chi Wei, Yuan-Chih Chu
  • Publication number: 20200335340
    Abstract: A method of manufacturing a semiconductor device including operations of forming a first hard mask over an underlying layer on a substrate by a photolithographic and etching method, forming a sidewall spacer pattern having a first sidewall portion and a second sidewall portion on opposing sides of the first hard mask, etching the first sidewall portion, etching the first hard mask and leaving the second sidewall portion bridging a gap of the etched first hard mask, and processing the underlying layer using the second hard mask.
    Type: Application
    Filed: July 6, 2020
    Publication date: October 22, 2020
    Inventors: Shih-Chun HUANG, Chiu-Hsiang CHEN, Ya-Wen YEH, Yu-Tien SHEN, Po-Chin CHANG, Chien Wen LAI, Wei-Liang LIN, Ya Hui CHANG, Yung-Sung YEN, Li-Te LIN, Pinyen LIN, Ru-Gun LIU, Chin-Hsiang LIN
  • Patent number: 10810121
    Abstract: A data merge method for a rewritable non-volatile memory module including a plurality of physical units is provided according to an exemplary embodiment of the disclosure. The method includes: obtaining a first logical distance value between a first physical unit and a second physical unit among the physical units, and the first logical distance value reflects a logical dispersion degree between at least one first logical unit mapped by the first physical unit and at least one second logical unit mapped by the second physical unit; and performing a data merge operation according to the first logical distance value, so as to copy valid from a source node to a recycling node.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: October 20, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Chien-Wen Chen, Ting-Wei Lin
  • Publication number: 20200328169
    Abstract: A method embodiment includes forming a sacrificial film layer over a top surface of a die, the die having a contact pad at the top surface. The die is attached to a carrier, and a molding compound is formed over the die and the sacrificial film layer. The molding compound extends along sidewalls of the die. The sacrificial film layer is exposed. The contact pad is exposed by removing at least a portion of the sacrificial film layer. A first polymer layer is formed over the die, and a redistribution layer (RDL) is formed over the die and electrically connects to the contact pad.
    Type: Application
    Filed: June 29, 2020
    Publication date: October 15, 2020
    Inventors: Chen-Hua Yu, Yen-Chang Hu, Ching-Wen Hsiao, Mirng-Ji Lii, Chung-Shi Liu, Chien Ling Hwang, Chih-Wei Lin, Chen-Shien Chen
  • Publication number: 20200309138
    Abstract: A fan module including a first body, a second body, a first fan assembly, a power module, and a second fan assembly is provided. The second body is slidably disposed at the first body to form a circulation space together. The first fan assembly is rotatably disposed at the first body and has sliding grooves. The power module is disposed in the first body and connected to the first fan assembly. The second fan assembly is rotatably disposed at the second body and has sliding portions, respectively and slidably disposed in corresponding sliding grooves. The power module is adapted to drive the first and second fan assemblies to rotate relative to the first body. A link module is adapted to drive the first and second bodies to relatively slide along an axial direction, so that the first and second fan assemblies are relatively separated or overlapped along the axial direction.
    Type: Application
    Filed: March 27, 2020
    Publication date: October 1, 2020
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Han-Hsuan Tsai, Jui-Min Huang, Wei-Hao Lan, Chien-Chu Chen, Ching-Ya Tu, Chih-Wen Chiang, Ching-Tai Chang, Ken-Ping Lin, Yao-Lin Chang, Cheng-Ya Chi
  • Patent number: 10777461
    Abstract: A method of manufacturing chip package is disclosed. The method includes steps of providing a wafer with an upper surface and a lower surface opposite thereto, in which a plurality of conductive pads are disposed on the upper surface; forming a plurality of conductive bumps on the corresponding conductive pads; thinning the wafer from the lower surface towards the upper surface; forming an insulating layer under the lower surface; etching the upper surface of the wafer to form a plurality of trenches exposing the insulating layer; forming a passivation layer covering an inner wall of each of the trenches; and dicing the passivation layer and the insulating layer along each of the trenches to form a plurality of chip packages.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: September 15, 2020
    Assignee: COMCHIP TECHNOLOGY CO., LTD.
    Inventors: Chien-Chih Lai, Hung-Wen Lin
  • Patent number: 10763148
    Abstract: A semiconductor defects inspection apparatus for inspection of bubble defects of an object is provided. The semiconductor defects inspection apparatus includes a carrier, an optical system, an infrared image capturing device, and a processing unit. The carrier is adapted for bearing the object. The optical system provides an illumination beam to the object to produce an image beam. The infrared image capturing device is disposed on a transmission path of the image beam. The infrared image capturing device is adapted for receiving the image beam to be transformed into an image information. The processing unit is electrically connected to the infrared image capturing device and adapted for analyzing the object according to the image information.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: September 1, 2020
    Assignee: UTECHZONE CO., LTD.
    Inventors: Chien-Wen Huang, Po-Tsung Lin, Chih-Heng Fang
  • Patent number: 10764475
    Abstract: A driving mechanism is provided, including a housing, a hollow frame, a holder, and a driving assembly. The frame is fixed to the housing and has a stop surface. The holder is movably disposed in the housing for holding the optical element. The driving assembly is disposed in the housing to drive the holder and the optical element moving along the optical axis of the optical element relative to the frame. Specifically, the stop surface is parallel to the optical axis to contact the holder and restrict the holder in a limit position.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: September 1, 2020
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Bing-Ru Song, Yi-Ho Chen, Chia-Pin Hsu, Chih-Wei Weng, Shin-Hua Chen, Chien-Lun Huang, Chao-Chun Chang, Shou-Jen Liu, Kun-Shih Lin, Nai-Wen Hsu, Yu-Cheng Lin, Shang-Yu Hsu, Yu-Huai Liao, Yi-Hsin Nieh, Shih-Ting Huang, Kuo-Chun Kao, Fu-Yuan Wu
  • Patent number: 10761653
    Abstract: A display panel able to receive full fingerprint impressions in a display area together with command touches, in addition to showing images, includes a substrate, scan lines, data lines, touch scan lines, touch lines, sub-pixels, and fingerprint sensing units. A method for driving such multifunctional touch display panel is also provided.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: September 1, 2020
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yu-Fu Weng, Chien-Wen Lin, Chia-Lin Liu
  • Publication number: 20200271890
    Abstract: A driving mechanism is provided and configured to drive an optical element. The driving mechanism includes a base unit, a holding unit, a driving assembly, a sensing assembly, and a first circuit component. The holding unit is configured to hold an optical element that has an optical axis. The driving assembly is configured to drive the optical element to move relative to the base unit. The sensing assembly is configured to detect the movement of the holding unit relative to the base unit. The first circuit component is disposed in the base unit and electrically connected to the sensing assembly, wherein the first circuit component extends in a direction that is substantially parallel to the optical axis.
    Type: Application
    Filed: May 13, 2020
    Publication date: August 27, 2020
    Inventors: Chien-Lun HUANG, Yu-Cheng LIN, Nai-Wen HSU
  • Patent number: 10741642
    Abstract: Embodiments of mechanisms for forming dislocations in source and drain regions of finFET devices are provided. The mechanisms involve recessing fins and removing the dielectric material in the isolation structures neighboring fins to increase epitaxial regions for dislocation formation. The mechanisms also involve performing a pre-amorphous implantation (PAI) process either before or after the epitaxial growth in the recessed source and drain regions. An anneal process after the PAI process enables consistent growth of the dislocations in the source and drain regions. The dislocations in the source and drain regions (or stressor regions) can form consistently to produce targeted strain in the source and drain regions to improve carrier mobility and device performance for NMOS devices.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: August 11, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Hsiung Tsai, Wei-Yuan Lu, Chien-Tai Chan, Wei-Yang Lee, Da-Wen Lin
  • Patent number: 10732757
    Abstract: A self-luminescence display apparatus capable of detecting pressure of touches applied by a user, the apparatus includes a display panel having a plurality of conductive layers and a supporting frame. One of the conductive layers cooperates with the supporting frame to form a plurality of force sensing capacitors. When a touch is applied, the display panel deforms according to pressure applied, which cause the capacitances of the force sensing capacitors to alter. The change in capacitance value, corresponding to a position where the touch operation is applied, can be calculated.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: August 4, 2020
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Chien-Wen Lin, Yu-Fu Weng, Chia-Lin Liu
  • Patent number: 10727113
    Abstract: A method includes providing a substrate comprising a material layer and a hard mask layer; patterning the hard mask layer to form hard mask lines; forming a spacer layer over the substrate, including over the hard mask lines, resulting in trenches defined by the spacer layer, wherein the trenches track the hard mask lines; forming a antireflective layer over the spacer layer, including over the trenches; forming an L-shaped opening in the antireflective layer, thereby exposing at least two of the trenches; filling the L-shaped opening with a fill material; etching the spacer layer to expose the hard mask lines; removing the hard mask lines; after removing the hard mask lines, transferring a pattern of the spacer layer and the fill material onto the material layer, resulting in second trenches tracking the pattern; and filling the second trenches with a conductive material.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: July 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ethan Hsiao, Chien Wen Lai, Chih-Ming Lai, Yi-Hsiung Lin, Cheng-Chi Chuang, Hsin-Ping Chen, Ru-Gun Liu