Abstract: A semiconductor device comprises semiconductor layers extending over a substrate, a gate structure, gate spacers, epitaxial source/drain structures, a conductive contact and a lower dielectric plug. The gate structure wraps around the semiconductor layers. The gate spacers are on opposite sidewalls of the gate structure. The epitaxial source/drain structures are on opposite sides of the metal gate structure. The conductive contact is over a first one of the epitaxial source/drain structures. The lower dielectric plug is over a second one of epitaxial source/drain structures, wherein from a cross-sectional view, the gate spacers are between the lower dielectric plug and the conductive contact, wherein from a plan view, the lower dielectric plug and the conductive contact have a same pattern.

Abstract: An optical test structure includes a substrate and at least one optical unit. The at least one optical unit is disposed on the substrate, and includes a first optical element, a second optical element, a third optical element, and a fourth optical element which are spaced apart from each other. The second optical element is disposed between the first optical element and the third optical element. The third optical element is disposed between the second optical element and the fourth optical element. A size of the third optical element is larger than a size of each of the first optical element, the second optical element, and the fourth optical element. The size of each of the second optical element and the fourth optical element is larger than the size of the first optical element.

Abstract: Optical modules and methods of forming the same are provided. In an embodiment, an exemplary method includes forming multiple first optical elements over a first wafer, forming multiple second optical elements over a second wafer, forming multiple third optical elements over a third wafer, aligning the first wafer with the second wafer such that, upon the aligning of the first wafer with the second wafer, each first optical element is vertically overlapped with a corresponding second optical element. The method also includes bonding the first wafer with the second wafer to form a first bonded structure, aligning the second wafer with the third wafer such that, and upon bonding the second wafer of the first bonded structure to the third wafer, where upon the aligning of the second wafer with the third wafer, each second optical element is vertically overlapped with a corresponding third optical element.

Abstract: A light field display system consists of a light field generator and a waveguide. The light field generator is configured to output a light field signal. The light field signal consists of a set of light beams. The waveguide is configured to diffract the set of light beams by the total internal reflection and to transmit the light field signal to a viewer.

Abstract: A data processing device includes a base plate and an electronic module. The base plate includes N driving portions. The electronic module includes an electronic component, a tray and a recognition mechanism. The tray is configured to support the electronic component and includes N slots. The tray is disposed on the base plate, such that an i-th driving portion of the N driving portions is disposed in an i-th slot of the N slots. The recognition mechanism is disposed on the tray. The recognition mechanism includes N interfering portions and N receiving recesses. When the tray moves with respect to the base plate toward a first direction, the i-th driving portion moves within the i-th slot toward a second direction to push an i-th interfering portion of the N interfering portions to move, such that the i-th interfering portion extends into an i-th receiving recess of the N receiving recesses.

Abstract: An image recognition method applied to an electronic device is provided. The method includes obtaining a recognition region and a plurality of test regions. A plurality of first prediction results is obtained by predicting each of the plurality of test regions using a first recognition model. A prediction accuracy rate is calculated. A plurality of target regions is obtained from the plurality of test regions, and a second recognition model is obtained by adjusting the first recognition model based on the prediction accuracy rate and the plurality of target regions. An initial feature matrix is obtained by inputting the recognition region in the second recognition model. A target vector is generated according to a target feature matrix and an initial weight matrix; and a recognition result of the image to be recognized is obtained by inputting the target vector into the second recognition model.

Abstract: A leakage gathering assembly includes a leakage gathering tray. The leakage gathering tray has a surface, a plurality of conveying channels, a convergent channel and a plurality of identification recesses. The conveying channels, the convergent channel and the identification recesses are recessed from the surface, the conveying channels communicate with the convergent channel, the identification recesses respectively communicate with the conveying channels, and depths of the identification recesses are greater than depths of the conveying channels.

Abstract: The disclosure provides a projection system and a projection method. The projection system includes a projection device. The projection device includes a projection module, a controller, and an audio player. The controller is coupled to the projection module. The audio player is coupled to the controller. When the controller executes the prepare-for-sleep mode, the controller operates the projection module to dim a projection beam or to project a predetermined projection image and operates the audio player to play a predetermined sound.

Abstract: An image detection and classification method for faster detection and classification by a neural network is applied to a neural network model including n operators. The neural network model is mapped to a singly-linked list. A vector of data pairs corresponding to the singly-linked list is established, and operator subsets of the neural network model are determined according to the vector. A target image is input to the neural network model, and input data and output data of the operator subset are recorded. The neural network model is applied to detect the target image, and a detection result is output according to the input data and the output data. The method can detect images quickly.

Abstract: A server includes a housing, a motherboard and at least one expansion module. The housing has an accommodation space and a front opening. The front opening is located at one side of the accommodation space and communicates with the accommodation space. The motherboard is located in the accommodation space and has at least one mainboard connector. The expansion module is removably disposed in the accommodation space and exposed to outside from the front opening. The expansion module includes a main body, a main connector and two fluid connectors. The main connector is disposed on the main body and removably assembled with the mainboard connector of the motherboard. The fluid connectors are disposed on the main body.

Abstract: A semiconductor device arrangement structure includes a carrier, semiconductor devices, and an adhesive layer. The semiconductor devices are separately disposed on the carrier, and each of the semiconductor devices includes an electrode. The adhesive layer is disposed between the carrier and the semiconductor devices, and the semiconductor devices are attached to the adhesive layer which is a continuous distributed single-layered structure. The adhesive layer includes unselected regions and a selected region, wherein the unselected regions are covered by the semiconductor devices respectively, and the selected region is not covered by the semiconductor devices. The adhesive layer further includes an indentation disposed on a surface of the selected region, and in a cross-sectional view or a top view, the contour of the indentation is a scaled copy of a contour of and the electrode, and the indentation has a depth less than that of the electrode.

Abstract: The present disclosure describes a semiconductor device having a dielectric structure between a source/drain (S/D) structure and a contact structure. The semiconductor device includes a S/D structure on a substrate, a dielectric structure on a top surface of the S/D structure, and a S/D contact structure on the S/D structure and the dielectric structure. A portion of the S/D contact structure is in contact with a top surface of the dielectric structure.

Abstract: A secondary-side controller applied to a flyback power converter prevents a secondary side of the flyback power converter from conducting incorrectly. The secondary-side controller includes a first comparison circuit, a second comparison circuit, and a gate control signal generation circuit. The first comparison circuit generates a first comparison signal according to a drain voltage of a synchronous switch of the secondary side of the flyback power converter and a first parameter. The second comparison circuit generates a ready signal according to the first comparison signal and a resistance of an external resistor. The gate control signal generation circuit generates a gate control signal to the synchronous switch according the ready signal and the drain voltage, and the synchronous switch is turned on according to the gate control signal.

Abstract: Reliable connector assembly and housing thereof. The housing may include a first portion having first spaces for receiving first connectors and a second portion having second spaces connected to the first spaces for receiving second connectors configured to mate with the first connectors. The first portion comprises a platform comprising a surface in a plane perpendicular to the mating direction at an interface of the first portion and the second portion. Such a configuration reduces the risk of exerting excessive force onto the connectors and increase the reliability of the connector assembly.

Abstract: The present disclosure provides a structure and method of fabricating the structure. The structure comprises a cavity enclosed by a first substrate and a second substrate opposite to the first substrate. Further, the structure includes a feature in the cavity and the feature is protruded from a surface of the first substrate. In addition, the structure includes a dielectric layer over the feature, wherein the dielectric layer includes a first surface in contact with the feature and a second surface opposite to the first surface is positioned toward the cavity.

Abstract: Disclosed is the source active region.

Abstract: A reliable socket connector. The connector includes an insulative body having a slot recessed from a mating face and terminals disposed in the insulative body having mating ends curving into the slot and tail ends extend thereout. A shell is disposed outside the insulative body. The shell has a mating portion extend beyond the mating face of the insulative body. The shell has a side wall comprising a docking portion and a guiding portion. The docking portion has holes configured for receiving a latch of a mating plug connector. The guiding portion extends beyond the docking portion in a mating direction and is configured for guiding the mating plug connector into the shell where a mating portion of the plug connector may then be guided into the slot of the insulative body.

Abstract: An LED arc display includes at least one LED matrix array module. Each LED matrix array module is composed of a plurality of LED matrix units arranged regularly. Each LED matrix unit includes a display surface, and the display surface has an outer contour. The outer contour is a non-quadrilateral. Therefore, a non-smooth visual experience caused by assembly tolerances of the plurality of LED matrix units can be improved by using non-quadrilateral outer contours of each LED matrix unit.

Abstract: Reliable connectors configured for easy locking/unlocking. A connector can include a first end configured to mate with a first mating component in a first direction, and a second end configured to mate with a second mating component in a second direction perpendicular to the first direction. The connector can include a locking member configured to move between locked and unlocked positions by a force applied in a third direction perpendicular to both the first and second directions. Such a configuration reduces the risk of interfering with connections between the mated components when applying the force and therefore provide more reliable connectors. The connectors can include a shell with a guiding structure to reduce the risk of damage to lightweight connectors that might otherwise be damaged due to misalignment during mating/unmating. Such a shell can be used with locking members configured for using within electronic systems with densely packed components.

Abstract: A method for manufacturing a semiconductor structure includes forming first and second fins over a substrate. The fin includes first and second semiconductor layers alternating stacked. The method further includes forming a dummy gate structure over the first and second fins, forming first source/drain features on opposite sides of the dummy gate structures and over the first fin, forming second source/drain features on opposite sides of the dummy gate structures and over the second fin, forming a dielectric layer over and between the first and second source/drain features, replacing the dummy gate structure and the first semiconductor layers with a gate structure wrapping around the first semiconductor layers, forming first silicide features over the first source/drain features, and forming second silicide features over the second source/drain features.