Patents by Inventor Chien-Yin Liu
Chien-Yin Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11935620Abstract: A memory device for memory cell programming and erasing with refreshing operation is disclosed. The memory device includes multiple location-related memory cells and a refresh module. The location-related memory cells are coupled to a bit line on which a selecting voltage is applied. The refresh module rewrites a stored data of a first cell of the location-related memory cells to the first cell of the location-related memory cells in response to an operation count being smaller than a number N. N is related to the number of the location-related memory cells.Type: GrantFiled: June 21, 2021Date of Patent: March 19, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yue-Der Chih, Cheng-Hsiung Kuo, Gu-Huan Li, Chien-Yin Liu
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Publication number: 20230385623Abstract: Disclosed is a methods and apparatus which can improve defect tolerability of a hardware-based neural network. In one embodiment, a method for performing a calculation of values on first neurons of a first layer in a neural network, includes: receiving a first pattern of a memory cell array; determining a second pattern of the memory cell array according to a third pattern; determining at least one pair of columns of the memory cell array according to the first pattern and the second pattern; switching input data of two columns of each of the at least one pair of columns of the memory cell array; and switching output data of the two columns in each of the at least one pair of columns of the memory cell array so as to determine the values on the first neurons of the first layer.Type: ApplicationFiled: August 8, 2023Publication date: November 30, 2023Inventors: Win-San KHWA, Yu-Der CHIH, Yi-Chun SHIH, Chien-Yin LIU
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Patent number: 11797831Abstract: Disclosed is a methods and apparatus which can improve defect tolerability of a hardware-based neural network. In one embodiment, a method for performing a calculation of values on first neurons of a first layer in a neural network, includes: receiving a first pattern of a memory cell array; determining a second pattern of the memory cell array according to a third pattern; determining at least one pair of columns of the memory cell array according to the first pattern and the second pattern; switching input data of two columns of each of the at least one pair of columns of the memory cell array; and switching output data of the two columns in each of the at least one pair of columns of the memory cell array so as to determine the values on the first neurons of the first layer.Type: GrantFiled: August 8, 2022Date of Patent: October 24, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Win-San Khwa, Yu-Der Chih, Yi-Chun Shih, Chien-Yin Liu
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Patent number: 11714717Abstract: A method of screening weak bits in a memory array includes dividing the memory array into a first and a second memory array, storing a first set of data in the first memory array, performing a first baking process on the first memory array or applying a first magnetic field to the first memory array, determining that a first portion of the first set of data stored in the first memory array is altered by the first baking process or the first magnetic field, and at least one of replacing memory cells of a first set of memory cells that are storing the first portion of the first set of data with corresponding memory cells in the second memory array of the memory array, or not using the memory cells of the first set of memory cells storing the first portion of the first set of data.Type: GrantFiled: March 24, 2022Date of Patent: August 1, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Der Chih, Chia-Fu Lee, Chien-Yin Liu, Yi-Chun Shih, Kuan-Chun Chen, Hsueh-Chih Yang, Shih-Lien Linus Lu
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Patent number: 11556414Abstract: A method includes: retrieving a first word comprising a plurality of data bits and a plurality of parity bits that correspond to the first word, wherein the plurality of data bits form N?1 groups and the plurality of parity bits form a first group different from the N?1 groups, and N is a positive integer greater than 2; receiving a request to update respective data bits of a first one of the N?1 groups; and providing a second word comprising updated data bits that form a second one of the N?1 groups and a plurality of updated parity bits that correspond to the second word, wherein the plurality of updated parity bits form a second group that has a same group index as the first one of the N?1 groups.Type: GrantFiled: April 5, 2021Date of Patent: January 17, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chien-Yin Liu, Yu-Der Chih, Hsueh-Chih Yang, Jonathan Tehan Chen, Kuan-Chun Chen
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Publication number: 20220383085Abstract: Disclosed is a methods and apparatus which can improve defect tolerability of a hardware-based neural network. In one embodiment, a method for performing a calculation of values on first neurons of a first layer in a neural network, includes: receiving a first pattern of a memory cell array; determining a second pattern of the memory cell array according to a third pattern; determining at least one pair of columns of the memory cell array according to the first pattern and the second pattern; switching input data of two columns of each of the at least one pair of columns of the memory cell array; and switching output data of the two columns in each of the at least one pair of columns of the memory cell array so as to determine the values on the first neurons of the first layer.Type: ApplicationFiled: August 8, 2022Publication date: December 1, 2022Inventors: Win-San Khwa, Yu-Der Chih, Yi-Chun Shih, Chien-Yin Liu
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Patent number: 11461623Abstract: Disclosed is a methods and apparatus which can improve defect tolerability of a hardware-based neural network. In one embodiment, a method for performing a calculation of values on first neurons of a first layer in a neural network, includes: receiving a first pattern of a memory cell array; determining a second pattern of the memory cell array according to a third pattern; determining at least one pair of columns of the memory cell array according to the first pattern and the second pattern; switching input data of two columns of each of the at least one pair of columns of the memory cell array; and switching output data of the two columns in each of the at least one pair of columns of the memory cell array so as to determine the values on the first neurons of the first layer.Type: GrantFiled: August 15, 2019Date of Patent: October 4, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Win-San Khwa, Yu-Der Chih, Yi-Chun Shih, Chien-Yin Liu
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Publication number: 20220214943Abstract: A method of screening weak bits in a memory array includes dividing the memory array into a first and a second memory array, storing a first set of data in the first memory array, performing a first baking process on the first memory array or applying a first magnetic field to the first memory array, determining that a first portion of the first set of data stored in the first memory array is altered by the first baking process or the first magnetic field, and at least one of replacing memory cells of a first set of memory cells that are storing the first portion of the first set of data with corresponding memory cells in the second memory array of the memory array, or not using the memory cells of the first set of memory cells storing the first portion of the first set of data.Type: ApplicationFiled: March 24, 2022Publication date: July 7, 2022Inventors: Yu-Der CHIH, Chia-Fu LEE, Chien-Yin LIU, Yi-Chun SHIH, Kuan-Chun CHEN, Hsueh-Chih YANG, Shih-Lien Linus LU
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Patent number: 11294764Abstract: A method of screening weak bits in a memory array. The method includes storing a first set of data in a first memory array of the memory array, performing a first baking process on at least the first memory array or applying a first magnetic field to at least the first memory array, tracking an address of at least a first memory cell of a first set of memory cells of the first memory array, if the first memory cell of the first set of memory cells stores altered data, and at least one of replacing the first memory cell of the first set of memory cells storing the altered data with a corresponding memory cell in a second memory array of the memory array, or discarding the first memory cell of the first set of memory cells storing the altered data.Type: GrantFiled: February 10, 2020Date of Patent: April 5, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Der Chih, Chia-Fu Lee, Chien-Yin Liu, Yi-Chun Shih, Kuan-Chun Chen, Hsueh-Chih Yang, Shih-Lien Linus Lu
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Patent number: 11264109Abstract: A circuit includes: writing a plurality of data words, each of which has a plurality of data bits, into respective bit cells of a memory device; in response to determining that not all the data bits of the plurality of data words are correctly written into the respective bit cells of the memory device, grouping the plurality of data words as a plurality of data word sets; and simultaneously rewriting a subset of data bits that were not correctly written into the respective bit cells of the memory device, wherein the subset of the data bits are contained in a respective one of the plurality of data word sets.Type: GrantFiled: December 3, 2020Date of Patent: March 1, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Der Chih, Chien-Yin Liu, Yi-Chun Shih
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Publication number: 20210312960Abstract: A memory device for memory cell programming and erasing with refreshing operation is disclosed. The memory device includes multiple location-related memory cells and a refresh module. The location-related memory cells are coupled to a bit line on which a selecting voltage is applied. The refresh module rewrites a stored data of a first cell of the location-related memory cells to the first cell of the location-related memory cells in response to an operation count being smaller than a number N. N is related to the number of the location-related memory cells.Type: ApplicationFiled: June 21, 2021Publication date: October 7, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yue-Der CHIH, Cheng-Hsiung KUO, Gu-Huan LI, Chien-Yin LIU
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Publication number: 20210224154Abstract: A method includes: retrieving a first word comprising a plurality of data bits and a plurality of parity bits that correspond to the first word, wherein the plurality of data bits form N?1 groups and the plurality of parity bits form a first group different from the N?1 groups, and N is a positive integer greater than 2; receiving a request to update respective data bits of a first one of the N?1 groups; and providing a second word comprising updated data bits that form a second one of the N?1 groups and a plurality of updated parity bits that correspond to the second word, wherein the plurality of updated parity bits form a second group that has a same group index as the first one of the N?1 groups.Type: ApplicationFiled: April 5, 2021Publication date: July 22, 2021Inventors: Chien-Yin LIU, Yu-Der CHIH, Hsueh-Chih YANG, Jonathan Tehan CHEN, Kuan-Chun CHEN
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Patent number: 11043249Abstract: A memory device for memory cell programming and erasing with refreshing operation is disclosed. The memory device includes a location-related memory cell and a refresh module. The location-related memory cell is coupled to a bit line. The refresh module is configured to refresh the location-related memory cell by reading data stored in the location-related memory cell and then writing the data back to the location-related memory cell in a condition that a target memory cell that is coupled to the bit line is programmed or erased. A method for memory cell programming and erasing with refreshing operation is also disclosed herein.Type: GrantFiled: November 6, 2019Date of Patent: June 22, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yue-Der Chih, Cheng-Hsiung Kuo, Gu-Huan Li, Chien-Yin Liu
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Patent number: 10970167Abstract: A method includes: retrieving a first word comprising a plurality of data bits and a plurality of parity bits that correspond to the first word, wherein the plurality of data bits form N?1 groups and the plurality of parity bits form a first group different from the N?1 groups, and N is a positive integer greater than 2; receiving a request to update respective data bits of a first one of the N?1 groups; and providing a second word comprising updated data bits that form a second one of the N?1 groups and a plurality of updated parity bits that correspond to the second word, wherein the plurality of updated parity bits form a second group that has a same group index as the first one of the N?1 groups.Type: GrantFiled: January 15, 2020Date of Patent: April 6, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien-Yin Liu, Yu-Der Chih, Hsueh-Chih Yang, Jonathan Tehan Chen, Kuan-Chun Chen
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Publication number: 20210090672Abstract: A circuit includes: writing a plurality of data words, each of which has a plurality of data bits, into respective bit cells of a memory device; in response to determining that not all the data bits of the plurality of data words are correctly written into the respective bit cells of the memory device, grouping the plurality of data words as a plurality of data word sets; and simultaneously rewriting a subset of data bits that were not correctly written into the respective bit cells of the memory device, wherein the subset of the data bits are contained in a respective one of the plurality of data word sets.Type: ApplicationFiled: December 3, 2020Publication date: March 25, 2021Inventors: Yu-Der CHIH, Chien-Yin LIU, Yi-Chun SHIH
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Patent number: 10861572Abstract: A circuit includes: writing a plurality of data words, each of which has a plurality of data bits, into respective bit cells of a memory device; in response to determining that not all the data bits of the plurality of data words are correctly written into the respective bit cells of the memory device, grouping the plurality of data words as a plurality of data word sets; and simultaneously rewriting a subset of data bits that were not correctly written into the respective bit cells of the memory device, wherein the subset of the data bits are contained in a respective one of the plurality of data word sets.Type: GrantFiled: April 23, 2020Date of Patent: December 8, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Der Chih, Chien-Yin Liu, Yi-Chun Shih
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Publication number: 20200251170Abstract: A circuit includes: writing a plurality of data words, each of which has a plurality of data bits, into respective bit cells of a memory device; in response to determining that not all the data bits of the plurality of data words are correctly written into the respective bit cells of the memory device, grouping the plurality of data words as a plurality of data word sets; and simultaneously rewriting a subset of data bits that were not correctly written into the respective bit cells of the memory device, wherein the subset of the data bits are contained in a respective one of the plurality of data word sets.Type: ApplicationFiled: April 23, 2020Publication date: August 6, 2020Inventors: Yu-Der Chih, Chien-Yin Liu, Yi-Chun Shih
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Publication number: 20200174883Abstract: A method of screening weak bits in a memory array. The method includes storing a first set of data in a first memory array of the memory array, performing a first baking process on at least the first memory array or applying a first magnetic field to at least the first memory array, tracking an address of at least a first memory cell of a first set of memory cells of the first memory array, if the first memory cell of the first set of memory cells stores altered data, and at least one of replacing the first memory cell of the first set of memory cells storing the altered data with a corresponding memory cell in a second memory array of the memory array, or discarding the first memory cell of the first set of memory cells storing the altered data.Type: ApplicationFiled: February 10, 2020Publication date: June 4, 2020Inventors: Yu-Der CHIH, Chia-Fu LEE, Chien-Yin LIU, Yi-Chun SHIH, Kuan-Chun CHEN, Hsueh-Chih YANG, Shih-Lien Linus LU
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Publication number: 20200151057Abstract: A method includes: retrieving a first word comprising a plurality of data bits and a plurality of parity bits that correspond to the first word, wherein the plurality of data bits form N?1 groups and the plurality of parity bits form a first group different from the N?1 groups, and N is a positive integer greater than 2; receiving a request to update respective data bits of a first one of the N?1 groups; and providing a second word comprising updated data bits that form a second one of the N?1 groups and a plurality of updated parity bits that correspond to the second word, wherein the plurality of updated parity bits form a second group that has a same group index as the first one of the N?1 groups.Type: ApplicationFiled: January 15, 2020Publication date: May 14, 2020Inventors: Chien-Yin Liu, Yu-Der Chih, Hsueh-Chih Yang, Jonathan Tehan Chen, Kuan-Chun Chen
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Patent number: 10643722Abstract: A circuit includes: writing a plurality of data words, each of which has a plurality of data bits, into respective bit cells of a memory device; in response to determining that not all the data bits of the plurality of data words are correctly written into the respective bit cells of the memory device, grouping the plurality of data words as a plurality of data word sets; and simultaneously rewriting a subset of data bits that were not correctly written into the respective bit cells of the memory device, wherein the subset of the data bits are contained in a respective one of the plurality of data word sets.Type: GrantFiled: October 12, 2018Date of Patent: May 5, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Der Chih, Chien-Yin Liu, Yi-Chun Shih