Abstract: Disclosed is a methods and apparatus which can improve defect tolerability of a hardware-based neural network. In one embodiment, a method for performing a calculation of values on first neurons of a first layer in a neural network, includes: receiving a first pattern of a memory cell array; determining a second pattern of the memory cell array according to a third pattern; determining at least one pair of columns of the memory cell array according to the first pattern and the second pattern; switching input data of two columns of each of the at least one pair of columns of the memory cell array; and switching output data of the two columns in each of the at least one pair of columns of the memory cell array so as to determine the values on the first neurons of the first layer.

Abstract: A method includes: retrieving a first word comprising a plurality of data bits and a plurality of parity bits that correspond to the first word, wherein the plurality of data bits form N?1 groups and the plurality of parity bits form a first group different from the N?1 groups, and N is a positive integer greater than 2; receiving a request to update respective data bits of a first one of the N?1 groups; and providing a second word comprising updated data bits that form a second one of the N?1 groups and a plurality of updated parity bits that correspond to the second word, wherein the plurality of updated parity bits form a second group that has a same group index as the first one of the N?1 groups.

Abstract: A memory device for memory cell programming and erasing with refreshing operation is disclosed. The memory device includes a location-related memory cell and a refresh module. The location-related memory cell is coupled to a bit line. The refresh module is configured to refresh the location-related memory cell by reading data stored in the location-related memory cell and then writing the data back to the location-related memory cell in a condition that a target memory cell that is coupled to the bit line is programmed or erased. A method for memory cell programming and erasing with refreshing operation is also disclosed herein.

Abstract: A method of correcting errors in a memory array. The method includes configuring a first memory array with a first error correction code (ECC) to provide error correction of data stored in the first memory array, configuring a second memory array with a second ECC to provide error correction of the data stored in the first memory array, performing a reflow process on the first and second memory array, and correcting data stored in the first memory array based on at least the first ECC or the second ECC. The first memory array includes a first set of memory cells arranged in rows and columns. The second memory array includes a second set of memory cells arranged in rows and columns.

Abstract: A memory device includes memory cells and a refresh module. The memory cells are coupled to a bit line, in which at least one memory cell of the memory cells is configured to store predetermined data. The refresh module is configured to refresh the at least one memory cell if a target memory cell of the memory cells is programmed or erased, in order to keep at least one cell current of the at least one memory cell away from a predetermined verify current level.

Abstract: A circuit includes: writing a plurality of data words, each of which has a plurality of data bits, into respective bit cells of a memory device; in response to determining that not all the data bits of the plurality of data words are correctly written into the respective bit cells of the memory device, grouping the plurality of data words as a plurality of data word sets; and simultaneously rewriting a subset of data bits that were not correctly written into the respective bit cells of the memory device, wherein the subset of the data bits are contained in a respective one of the plurality of data word sets.

Abstract: A method includes: retrieving a first word comprising a plurality of data bits and a plurality of parity bits that correspond to the first word, wherein the plurality of data bits form N?1 groups and the plurality of parity bits form a first group different from the N?1 groups, and N is a positive integer greater than 2; receiving a request to update respective data bits of a first one of the N?1 groups; and providing a second word comprising updated data bits that form a second one of the N?1 groups and a plurality of updated parity bits that correspond to the second word, wherein the plurality of updated parity bits form a second group that has a same group index as the first one of the N?1 groups.

Abstract: The present disclosure discloses a data storage device having error detection and correction capabilities. The data storage device includes an information encoder/decoder having error checking circuitry to determine whether one or more errors present in an input datastream. When the one or more errors are present in the input datastream, the information encoder/decoder activates error correction circuitry to correct the one or more errors when present in the input datastream. Otherwise, when the one or more errors are not present in the input datastream, the information encoder/decoder deactivates the error correction circuitry. This activation and deactivation conserves power when compared to conventional data storage devices. Any error correction circuitry, if present, in these conventional data storage devices continuously remain active even when the one or more errors are not present in the input datastream.

Abstract: A memory device includes memory cells and a refresh module. The memory cells are coupled to a bit line, in which at least one memory cell of the memory cells is configured to store predetermined data. The refresh module is configured to refresh the at least one memory cell if a target memory cell of the memory cells is programmed or erased, in order to keep at least one cell current of the at least one memory cell away from a predetermined verify current level.

Abstract: A method of correcting errors in a memory array. The method includes configuring a first memory array with a first error correction code (ECC) to provide error correction of data stored in the first memory array, configuring a second memory array with a second ECC to provide error correction of the data stored in the first memory array, performing a reflow process on the first and second memory array, and correcting data stored in the first memory array based on at least the first ECC or the second ECC. The first memory array includes a first set of memory cells arranged in rows and columns. The second memory array includes a second set of memory cells arranged in rows and columns.

Abstract: The present disclosure discloses a data storage device having error detection and correction capabilities. The data storage device includes an information encoder/decoder having error checking circuitry to determine whether one or more errors present in an input datastream. When the one or more errors are present in the input datastream, the information encoder/decoder activates error correction circuitry to detect a location one to correct the one or more errors when present in the input datastream. Otherwise, when the one or more errors are not present in the input datastream, the information encoder/decoder deactivates the error correction circuitry. This activation and deactivation conserves power when compared to conventional data storage devices. Any error correction circuitry, if present, in these conventional data storage devices continuously remain active even when the one or more errors are not present in the input datastream.

Abstract: A method and a system for memory cell programming and erasing with refreshing operation are disclosed. The system includes a selecting module, a processing module and a refresh module. In the method, at first, a target memory cell from a plurality of memory cells in a memory device is selected. Thereafter, the target memory cell belonging to a line of the matrix is programmed or erased by applying a selecting voltage on the target memory cell and a location-related memory cell belonging to the line of the matrix. Then, a refreshing operation to refresh the location-related cell is performed.

Abstract: A method and a system for memory cell programming and erasing with refreshing operation are disclosed. The system includes a selecting module, a processing module and a refresh module. In the method, at first, a target memory cell from a plurality of memory cells in a memory device is selected. Thereafter, the target memory cell belonging to a line of the matrix is programmed or erased by applying a selecting voltage on the target memory cell and a location-related memory cell belonging to the line of the matrix. Then, a refreshing operation to refresh the location-related cell is performed.

Abstract: A method and a system for memory cell programming and erasing with refreshing operation are disclosed. The system includes a selecting module, a processing module and a refresh module. In the method, at first, a target memory cell from a plurality of memory cells in a memory device is selected. Thereafter, the target memory cell belonging to a line of the matrix is programmed or erased by applying a selecting voltage on the target memory cell and a location-related memory cell belonging to the line of the matrix.

Abstract: A method and a system for memory cell programming and erasing with refreshing operation are disclosed. The system includes a selecting module, a processing module and a refresh module. In the method, at first, a target memory cell from a plurality of memory cells in a memory device is selected. Thereafter, the target memory cell belonging to a line of the matrix is programmed or erased by applying a selecting voltage on the target memory cell and a location-related memory cell belonging to the line of the matrix.

Abstract: A method and a system for memory cell programming and erasing with refreshing operation are disclosed. The system includes a selecting module, a processing module and a refresh module. In the method, at first, a target memory cell from a plurality of memory cells in a memory device is selected. Thereafter, the target memory cell belonging to a line of the matrix is programmed or erased by applying a selecting voltage on the target memory cell and a location-related memory cell belonging to the line of the matrix. Then, a refreshing operation to refresh the location-related cell is performed.

Abstract: A method and a system for memory cell programming and erasing with refreshing operation are disclosed. The system includes a selecting module, a processing module and a refresh module. In the method, at first, a target memory cell from a plurality of memory cells in a memory device is selected. Thereafter, the target memory cell belonging to a line of the matrix is programmed or erased by applying a selecting voltage on the target memory cell and a location-related memory cell belonging to the line of the matrix. Then, a refreshing operation to refresh the location-related cell is performed.

Abstract: A method for page random write and read in blocks of flash memory is disclosed. The data could be random written in the pages of block. The pages would be arranged when the block was filled with data, so as to prevent from data copied and erased repeatedly. Present invention would reduce the data read/write time and increase the life-span of flash memory.

Abstract: A method for page random write and read in blocks of flash memory is disclosed. The data could be random written in the pages of block. The pages would be arranged when the block was filled with data, so as to prevent from data copied and erased repeatedly. Present invention would reduce the data read/write time and increase the life-span of flash memory.

Abstract: Data accessing structure and method for flash memory is disclosed. While data copying is performed in flash memory, a main controller assigns some of buffers as copy buffers; when data copying is not performed in flash memory, the main controller assigns all of buffers as data buffers. Therefore, all of buffers in a flash memory card are totally utilized.