Abstract: A microphone system is disclosed, comprising: a microphone array and a processing unit. The microphone array comprises Q microphones that detect sound and generate Q audio signals. The processing unit is configured to perform operations comprising: spatial filtering over the Q audio signals using a trained model based on at least one target beam area (TBA) and coordinates of the Q microphones to generate a beamformed output signal originated from ? target sound source inside the at least one TBA, where ?>=0. Each TBA is defined by r time delay ranges for r combinations of two microphones out of the Q microphones, where Q>=3 and r>=1. A dimension of a first number for locations of all sound sources able to be distinguished by the processing unit increases as a dimension of a second number for a geometry formed by the Q microphones increases.

Abstract: An inductor circuit includes a receiver inductive circuit, a transmitter inductive circuit, and an antenna inductive circuit which are implemented on a single chip die; the receiver inductive circuit is disposed on a specific ring of a specific plane to form a ring shape; the transmitter inductive circuit and the antenna inductive circuit are disposed inside the specific ring and surrounded by the specific ring of the specific plane; and, a circuit area, occupied by the transmitter inductive circuit, inside the specific ring and on the specific plane, is larger than a circuit area occupied by the receiver inductive circuit and by the antenna inductive circuit.

Abstract: A method of enhancing IP packet forwarding feature support after interworking is proposed. When a PDU session in 5GS is transferred to a PDN connection in EPS, the UE shall assume the feature is supported after inter-system change from 5GS to EPS. When a PDN connection is established in EPS, the network indicated that the feature is not supported, and the network provided 5GSM parameters for ESM/5GSM interworking for this PDN connection, then UE shall assume the feature is supported after inter-system change from EPS to 5GS, the UE shall also assume the feature is supported after inter-system change from 5GS back to EPS. The IP packet forwarding features include PS data off and local IP address in TFT.

Abstract: A light-emitting device includes a substrate with a top surface; a first light-emitting structure unit and a second light-emitting structure unit separately formed on the top surface and adjacent to each other, and wherein the first light-emitting structure unit includes a first sidewall and the second light-emitting structure unit includes a second sidewall; an isolation layer formed on the first sidewall and the second sidewall, including a first edge on the first light-emitting structure unit and wherein the first edge has an acute angle in a cross-sectional view; and an electrical connection formed on the isolation layer, the first light-emitting structure unit and the second light-emitting structure unit, and electrically connecting the first light-emitting structure unit and the second light-emitting structure unit; wherein the first sidewall and the second sidewall are inclined; and wherein the electrical connection includes a first part on the first light-emitting structure unit, and the first part do

Abstract: An actuator includes a casing, an output disc, a transmission component, a cable, a power source, and a tension adjustment assembly. The output disc and the transmission component are rotatably disposed on the casing. The cable is disposed through the transmission component and connected to the output disc. The power source can drive the transmission component. The tension adjustment assembly includes a lever, an elastic component, and a slidable component. The lever has a first end and a second end opposite to each other. The first end is connected to the cable. The elastic component is connected to the casing and the second end of the lever. The slidable component is in contact with a portion of the lever located between the first end and the second end, and is slidable along the lever to change its position to adjust a tension of the cable.

Abstract: A memory device includes a bit line, a word line, a memory cell including a capacitor and a transistor, and a controller. The transistor has a gate terminal coupled to the word line, a first terminal, and a second terminal. The capacitor has a first end coupled to the first terminal of the transistor, a second end coupled to the bit line, and an insulating material between the first end and the second end. The controller, in a programming operation, applies a turn-ON voltage via the word line to the gate terminal of the transistor to turn ON the transistor, and applies a program voltage via the bit line to the second end of the capacitor to apply, while the transistor is turned ON, a predetermined break-down voltage or higher between the first end and the second end of the capacitor to break down the insulating material of the capacitor.

Abstract: A one-time programmable (OTP) bit cell includes a substrate including a front side and a back side, an active area on the front side, a first read transistor including a first gate and a first portion of the active area intersected by the first gate, a program transistor including a second gate and a second portion of the active area intersected by the second gate, a first electrical connection to the first gate, a second electrical connection to the second gate, and a third electrical connection to the active area. At least one of the first, second, or third electrical connections includes a metal line positioned on the back side.

Abstract: An integrated circuit includes a front-side horizontal conducting line in a first metal layer, a front-side vertical conducting line in a second metal layer, a front-side fuse element, and a backside conducting line. The front-side horizontal conducting line is directly connected to the drain terminal-conductor of a transistor through a front-side terminal via-connector. The front-side vertical conducting line is directly connected to the front-side horizontal conducting line through a front-side metal-to-metal via-connector. The front-side fuse element having a first fuse terminal conductively connected to the front-side vertical conducting line. The backside conducting line is directly connected to the source terminal-conductor of the transistor through a backside terminal via-connector.

Abstract: A method (of manufacturing a semiconductor device) includes: forming via structures in a first via layer over a transistor layer; forming a first via structure of a first deep via arrangement in the first via layer; forming conductive segments in a first metallization layer over the first via layer; forming M_1st routing segments at least a majority of which, relative to a first direction, have corresponding long axes with lengths which at least equal if not exceed a first permissible minimum value for routing segments in the first metallization layer; forming an M_1st interconnection segment having a long axis which is less than the first permissible minimum value and which is included in the first deep via arrangement; and forming via structures in a second via layer over the first metallization layer, including forming a first via structure of the first deep via arrangement in the second via layer.

Abstract: The present disclosure provides a thickness measuring device including a base, a first moving component, a second moving component, a frame and a linking component. The base includes a base main body and a sensor. The first moving component moves along a first direction and includes a contacting end. The second moving component moves along a second direction and includes a sensing element corresponding to the sensor. The frame is connected to the base and includes a frame main body, a first guiding groove and a second guiding groove. The first and second guiding grooves are formed on the frame main body for accommodating the first and second moving components. The linking component includes a rotating element, a first connection portion and a second connection portion. The first and second connection portions are disposed on a surface of the rotating element and connected to the first and second moving components.

Abstract: A method of manufacturing a semiconductor device includes: generating a design data of the semiconductor device; and generating a design layout according to the design data. The design layout includes: a first power rail; a second power rail; a first cell including a first first-type active region and a first second-type active region, wherein a first cell height of the first cell is defined as a pitch between the first power rail and the second power rail; a second cell having a second first-type active region and a second second-type active region; and a third cell having a first portion and a second portion arranged in the second row and a fourth row, respectively.

Abstract: A memory device includes at least one bit line, at least one word line, and at least one memory cell comprising a capacitor and a transistor. The transistor has a gate terminal coupled to the word line, a first terminal, and a second terminal. The capacitor has a first end coupled to the first terminal of the transistor, a second end coupled to the bit line, and an insulating material between the first end and the second end. The insulating material is configured to break down under a predetermined break-down voltage or higher applied between the first end and the second end.

Abstract: An antifuse structure and IC devices incorporating such antifuse structures in which the antifuse structure includes an dielectric antifuse structure formed on an active area having a first dielectric antifuse electrode, a second dielectric antifuse electrode extending parallel to the first dielectric antifuse electrode, a first dielectric composition between the first dielectric antifuse electrode and the second dielectric antifuse electrode, and a first programming transistor electrically connected to a first voltage supply wherein, during a programming operation a programming voltage is selectively applied to certain of the dielectric antifuse structures to form a resistive direct electrical connection between the first dielectric antifuse electrode and the second dielectric antifuse electrode.

Abstract: An IC device includes a first active area extending away from a first endpoint in a first direction, a second active area extending away from a second endpoint in the first direction, a third active area positioned between the first and second active areas, and a gate structure perpendicular to the first through third active areas. The gate structure overlies each of the first and second endpoints and the third active area, and the third active area extends away from the gate structure in a second direction opposite the first direction.

Abstract: An IC device includes first through third device pairs positioned in first through third active areas extending in a first direction, each pair including first and second transistors coupled between respective first and second anti-fuse structures and a shared bit line contact, and each of the first and third active areas being adjacent to the second active area. First through fourth conductive lines extend in a second direction, first and second conductive paths couple the first conductive line to the first anti-fuse structures, a third conductive path couples the fourth conductive line to the second anti-fuse structures, and a fourth conductive path couples the third conductive line to the second transistors. The first and third conductive paths are aligned along the first direction between the first and second active areas, and the second and fourth conductive paths are aligned along the first direction between the second and third active areas.

Abstract: A memory device is disclosed. The memory device includes a first transistor and a first capacitor electrically coupled to the first transistor, the first transistor and the first capacitor forming a first one-time-programmable (OTP) memory cell. The first capacitor has a first bottom metal terminal, a first top metal terminal, and a first insulation layer interposed between the first bottom and first top metal terminals. The first insulation layer comprises a first portion, a second portion separated from the first portion, and a third portion vertically extending between the first portion and the second portion. The first bottom metal terminal is directly below and in contact with the first portion of the first insulation layer.

Abstract: A method of generating a layout diagram of an IC cell includes defining a boundary recess in a boundary of the cell by extending a first portion of the boundary along a first gate track, extending a second portion of the boundary from the first gate track to a second gate track, the second portion being contiguous with the first portion, and extending a third portion of the boundary from the first gate track to the second gate track, the third portion being contiguous with the first portion. An active region is positioned in the cell by extending the active region across a third gate track, wherein the first gate track is between the second gate track and the third gate track. The layout diagram is stored on a non-transitory computer-readable medium.

Abstract: A method of generating an IC layout diagram includes positioning a first active region between second and third active regions, intersecting the first active region with first through fourth gate regions to define gate locations of first and second anti-fuse bits, aligning first and second conductive regions between the first and second active regions, thereby intersecting the first conductive region with the first gate region and the second conductive region with the fourth gate region, and aligning third and fourth conductive regions between the first and third active regions, thereby either intersecting the third and fourth conductive regions with the first and third gate regions, or intersecting the third and fourth conductive regions with the second and fourth gate regions. At least one of positioning or intersecting the first active region, or aligning the first and second or third and fourth conductive regions is executed by a processor.

Abstract: The present disclosure provides a thickness measuring device including a base, a first moving component, a second moving component, a frame and a linking component. The base includes a base main body and a sensor. The first moving component moves along a first direction and includes a contacting end. The second moving component moves along a second direction and includes a sensing element corresponding to the sensor. The frame is connected to the base and includes a frame main body, a first guiding groove and a second guiding groove. The first and second guiding grooves are formed on the frame main body for accommodating the first and second moving components. The linking component includes a rotating element, a first connection portion and a second connection portion. The first and second connection portions are disposed on a surface of the rotating element and connected to the first and second moving components.

Abstract: A memory device includes at least one bit line, at least one word line, and at least one memory cell comprising a capacitor and a transistor. The transistor has a gate terminal coupled to the word line, a first terminal, and a second terminal. The capacitor has a first end coupled to the first terminal of the transistor, a second end coupled to the bit line, and an insulating material between the first end and the second end. The insulating material is configured to break down under a predetermined break-down voltage or higher applied between the first end and the second end.