Abstract: An IC device includes first through third active areas extending in a first direction and a first gate structure extending perpendicular to and overlying each of the first through third active areas. Each of the first through third active areas includes a first portion adjacent to the first gate structure in the first direction and a second portion adjacent to the first portion and including an endpoint of the corresponding active area, the first active area is positioned between the second and third active areas and includes the endpoint positioned under the first gate structure, and each of the second and third active areas includes the endpoint positioned away from the gate structure in a second direction opposite to the first direction.

Abstract: A microphone system for a boomless headset is disclosed, comprising a microphone array and a processing unit. The microphone array comprises Q microphones and generates Q audio signals. A first microphone and a second microphone are disposed on different earcups, and a third microphone is disposed on one of two earcups and displaced laterally and vertically from one of the first and the second microphones. The processing unit performs operations comprising: performing spatial filtering over the Q audio signals using a trained model based on an arc line with a vertical distance and a horizontal distance from a midpoint between the first and the second microphones, a time delay range for the first and the second microphones and coordinates of the Q microphones to generate a beamformed output signal originated from zero or more target sound sources inside a target beam area, where Q>=3.

Abstract: A semiconductor device includes a transistor layer, a first via layer over the transistor layer, a first metallization layer over the first via layer, the first metallization layer including first conductors having long axes extending substantially in a first direction, a second via layer over the first metallization layer, and a conductive deep via extending in the second via layer, the first metallization layer, and the first via layer. The first conductors represent a majority of conductive material in the first metallization layer, and a size of the deep via in the first direction in the first metallization layer is substantially less than a minimum length of the first conductors in the first metallization layer.

Abstract: An ultraviolet (UV) sterilization system and monitoring method are applied to detect the working state of each UV lamp tube in an autonomous mobile robot. The monitoring method for UV sterilization includes enabling the autonomous mobile robot to move at a travel speed, driving the UV lamp to illuminate an UV, fetching an inductive voltage for each UV lamp, generating a report according to the inductive voltages for each UV lamp, and sending the report to a monitor server via the network from the autonomous mobile robot. Therefore, the monitoring server can check and record the working state of each UV lamp according to the report, and further the monitoring server will transmit a notification message to a client when the working state of any UV lamp is abnormal.

Abstract: A semiconductor device includes a memory array comprising a plurality of transistors arranged over a plurality of rows and a plurality of columns. The plurality of rows correspond to a plurality of active regions that continuously extend along a first lateral direction, respectively, and the plurality of columns correspond to a plurality of gate structures that discontinuously extend along a second lateral direction, respectively, the first lateral direction and the second lateral direction being perpendicular to each other. A first one of the gate structures comprising a first gap cutting the first gate structure and a second one of the gate structures comprising a second gap cutting the second gate structure are disposed immediately next to each other along the first lateral direction. The first gap and an extension of the second gap are offset from each other along the second lateral direction.

Abstract: An integrated circuit includes a front-side horizontal conducting line and a front-side vertical conducting line at the front side of the substrate, a transistor in a semiconductor structure at the front side of the substrate, and a backside conducting line at a backside of the substrate. The front-side horizontal conducting line is directly connected to a first terminal of the transistor through a front-side terminal via-connector and directly connected to the front-side horizontal conducting line through a front-side metal-to-metal via-connector. A word connection line directly is connected to a gate terminal of the transistor through a gate via-connector. The backside conducting line is directly connected to a second terminal of the transistor through a backside terminal via-connector. In the integrated circuit, a front-side fuse element is conductively connected to either the front-side vertical conducting line or the front-side horizontal conducting line.

Abstract: A semiconductor device includes: a first row, a second row and a third row extending in a row direction and arranged in a column direction; a first power rail extending in the row direction between the first row and the second row, and configured to supply a first voltage; a second power rail extending in the row direction between the second row and the third row, and configured to supply a second voltage different from the first voltage; and a split cell comprising a first portion and a second portion arranged in the first row and the third row, respectively.

Abstract: A method of generating an IC layout diagram includes abutting first and second cells to define a first active region including first and second anti-fuse bits, abutting third and fourth cells to define a second active region including third and fourth anti-fuse bits, and defining a third active region including fifth and sixth anti-fuse bits adjacent to the first through fourth anti-fuse bits. The first cell includes first and second via regions overlapping first and second gate regions shared by respective structures and transistors of the first, third, and fifth anti-fuse bits, the fourth cell includes third and fourth via regions overlapping third and fourth gate regions shared by respective transistors and structures of the second, fourth, and sixth anti-fuse bits, the third cell includes fifth and sixth via regions overlapping the first gate region, and the second cell includes seventh and eighth via regions overlapping the fourth gate region.

Abstract: An integrated circuit includes a transistor formed in a semiconductor structure, a front-side horizontal conducting line in a first metal layer above the semiconductor structure, and a front-side vertical conducting line in a second metal layer above the first metal layer. The front-side horizontal conducting line is directly connected to a first terminal of the transistor, and the front-side vertical conducting line is directly connected to the front-side horizontal conducting line. In the integrated circuit, a front-side fuse element is conductively connected to the front-side vertical conducting line, and a backside conducting line is directly connected to a second terminal of the transistor. A word connection line extending in the first direction is directly connected to a gate terminal of the transistor.

Abstract: A method of manufacturing a semiconductor device includes: generating a design data of the semiconductor device; and generating a design layout according to the design data. The design layout includes: a first power rail; a second power rail; a first cell including a first first-type active region and a first second-type active region, wherein a first cell height of the first cell is defined as a pitch between the first power rail and the second power rail; a second cell having a second first-type active region and a second second-type active region; and a third cell having a first portion and a second portion arranged in the second row and a fourth row, respectively.

Abstract: A method of generating an integrated circuit (IC) layout diagram includes overlapping an active region with a plurality of gate regions, thereby defining a program transistor and a read transistor of a one-time-programmable (OTP) bit, overlapping a through via region with a gate region of the plurality of gate regions or with the active region, and overlapping the through via region with a metal region of a back-side metal layer.

Abstract: An antifuse structure and IC devices incorporating such antifuse structures in which the antifuse structure includes an dielectric antifuse structure formed on an active area having a first dielectric antifuse electrode, a second dielectric antifuse electrode extending parallel to the first dielectric antifuse electrode, a first dielectric composition between the first dielectric antifuse electrode and the second dielectric antifuse electrode, and a first programming transistor electrically connected to a first voltage supply wherein, during a programming operation a programming voltage is selectively applied to certain of the dielectric antifuse structures to form a resistive direct electrical connection between the first dielectric antifuse electrode and the second dielectric antifuse electrode.

Abstract: A semiconductor device includes a transistor layer, a first via layer over the transistor layer, a first metallization layer over the first via layer, the first metallization layer including first conductors having long axes extending substantially in a first direction, a second via layer over the first metallization layer, and a conductive deep via extending in the second via layer, the first metallization layer, and the first via layer. The first conductors represent a majority of conductive material in the first metallization layer, and a size of the deep via in the first direction in the first metallization layer is substantially less than a minimum length of the first conductors in the first metallization layer.

Abstract: An integrated circuit includes a transistor formed in a semiconductor structure, a front-side horizontal conducting line in a first metal layer above the semiconductor structure, and a front-side vertical conducting line in a second metal layer above the first metal layer. The front-side horizontal conducting line is directly connected to a first terminal of the transistor, and the front-side vertical conducting line is directly connected to the front-side horizontal conducting line. In the integrated circuit, a front-side fuse element is conductively connected to the front-side vertical conducting line, and a backside conducting line is directly connected to a second terminal of the transistor. A word connection line extending in the first direction is directly connected to a gate terminal of the transistor.

Abstract: A one-time programmable (OTP) bit cell includes a substrate including a front side and a back side, an active area on the front side, a first read transistor including a first gate and a first portion of the active area intersected by the first gate, a program transistor including a second gate and a second portion of the active area intersected by the second gate, a first electrical connection to the first gate, a second electrical connection to the second gate, and a third electrical connection to the active area. At least one of the first, second, or third electrical connections includes a metal line positioned on the back side.

Abstract: An antifuse structure and IC devices incorporating such antifuse structures in which the antifuse structure includes an dielectric antifuse structure formed on an active area having a first dielectric antifuse electrode, a second dielectric antifuse electrode extending parallel to the first dielectric antifuse electrode, a first dielectric composition between the first dielectric antifuse electrode and the second dielectric antifuse electrode, and a first programming transistor electrically connected to a first voltage supply wherein, during a programming operation a programming voltage is selectively applied to certain of the dielectric antifuse structures to form a resistive direct electrical connection between the first dielectric antifuse electrode and the second dielectric antifuse electrode.

Abstract: A method of manufacturing a semiconductor device includes forming via structures in a first via layer over a transistor layer, the forming the via structures in the first via layer including forming a first via structure in the first via layer, the first via structure being included in a first deep via arrangement; forming conductive segments in a first metallization layer over the first via layer, the forming the conductive segments in the first metallization layer including forming M_1st routing segments at least a majority of which, relative to a first direction, have corresponding long axes with lengths which at least equal if not exceed a first permissible minimum value for routing segments in the first metallization layer; and forming an M_1st interconnection segment having a long axis which is less than the first permissible minimum value, the M_1st interconnection segment being included in the first deep via arrangement.

Abstract: An integrated circuit includes a front-side horizontal conducting line in a first metal layer, a front-side vertical conducting line in a second metal layer, a front-side fuse element, and a backside conducting line. The front-side horizontal conducting line is directly connected to the drain terminal-conductor of a transistor through a front-side terminal via-connector. The front-side vertical conducting line is directly connected to the front-side horizontal conducting line through a front-side metal-to-metal via-connector. The front-side fuse element having a first fuse terminal conductively connected to the front-side vertical conducting line. The backside conducting line is directly connected to the source terminal-conductor of the transistor through a backside terminal via-connector.

Abstract: An IC device includes first through third active areas extending in a first direction and a first gate structure extending perpendicular to and overlying each of the first through third active areas. Each of the first through third active areas includes a first portion adjacent to the first gate structure in the first direction and a second portion adjacent to the first portion and including an endpoint of the corresponding active area, the first active area is positioned between the second and third active areas and includes the endpoint positioned under the first gate structure, and each of the second and third active areas includes the endpoint positioned away from the gate structure in a second direction opposite to the first direction.

Abstract: A semiconductor device includes a first power rail configured to supply a first voltage, a second power rail configured to supply a second voltage different from the first voltage, and a first cell arranged in a first row between the first and second power rails. The first cell has a first first-type active region and a first second-type active region. The semiconductor device further includes a second cell having a second first-type active region and a second second-type active region, wherein the second first-type active region extends in a second row and a third row on a first side of the first row. The semiconductor device also includes a third cell including a first portion and a second portion, wherein the first portion and the second portion are arranged on two sides of the first cell.