Patents by Inventor Chien-Ying WU
Chien-Ying WU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12169308Abstract: A method of using a coupling system includes aligning an optical fiber with a cavity in a chip, wherein aligning the optical fiber comprises orienting the fiber within an angle ranging from about 88-degrees to about 92-degrees with respect to a top surface of the chip. The method further includes emitting an optical signal from the optical fiber. The method further includes redirecting the optical signal into a waveguide using a grating positioned on an opposite side of the cavity from the optical fiber.Type: GrantFiled: August 10, 2023Date of Patent: December 17, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Sui-Ying Hsu, Yuehying Lee, Chien-Ying Wu, Chen-Hao Huang, Chien-Chang Lee, Chia-Ping Lai
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Publication number: 20240393531Abstract: A method of fabricating a photonic device includes: forming a photonic device structure that includes a SOI substrate, which includes a bulk substrate layer, a buried oxide layer on the bulk substrate layer and an active semiconductor layer on the buried oxide layer; forming an electrically conducting layer in electrical contact of the buried oxide layer, and forming a BEOL structure on a surface of the active silicon layer.Type: ApplicationFiled: July 31, 2024Publication date: November 28, 2024Applicant: Taiwan Semiconductor Manufacturing Company Ltd.Inventors: Yueh Ying Lee, Tzu-Chung Tsai, Chien-Ying Wu, Jhih-Ming Lin
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Patent number: 12153255Abstract: A method of making a photonic device includes depositing a cladding layer over a silicon layer. The method further includes patterning the cladding layer to expose a first portion of the silicon layer, wherein a second portion of the silicon layer is covered by the patterned cladding layer, and a waveguide portion is in the second portion of the silicon layer. The method further includes depositing a low refractive index layer directly over the patterned cladding layer, wherein a refractive index of the low refractive index layer is less than a refractive index of silicon nitride.Type: GrantFiled: August 10, 2023Date of Patent: November 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chien-Ying Wu, Yuehying Lee, Sui-Ying Hsu, Chen-Hao Huang, Chien-Chang Lee, Chia-Ping Lai
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Publication number: 20240361532Abstract: A coupling system includes an optical fiber configured to carry an optical signal. The coupling system further includes a grating on a first side of a semiconductor layer, wherein the grating is configured to receive the optical signal. The coupling system further includes an interconnect structure over the grating on the first side of the semiconductor layer, wherein the interconnect structure defines a cavity aligned with the grating. The coupling system further includes a first polysilicon layer on a second side of the semiconductor layer, wherein the second side of the semiconductor layer is opposite to the first side of the semiconductor layer.Type: ApplicationFiled: July 10, 2024Publication date: October 31, 2024Inventors: Chen-Hao HUANG, Hau-Yan LU, Sui-Ying HSU, Yuehying LEE, Chien-Ying WU, Chien-Chang LEE, Chia-Ping LAI
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Patent number: 12072534Abstract: A coupling system includes an optical fiber configured to carry an optical signal. The coupling system further includes a chip in optical communication with the optical fiber. An angle between the optical fiber and a top surface of the chip ranges from about 92-degrees to about 88-degrees. The chip includes a grating configured to receive the optical signal; and a waveguide, wherein the grating is configured to receive the optical signal and redirect the optical signal along the waveguide. ms.Type: GrantFiled: August 27, 2021Date of Patent: August 27, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Sui-Ying Hsu, Yuehying Lee, Chien-Ying Wu, Chen-Hao Huang, Chien-Chang Lee, Chia-Ping Lai
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Patent number: 12050348Abstract: A method of making a chip includes depositing a first polysilicon layer on a top surface and a bottom surface of a substrate. The method further includes patterning the first polysilicon layer to define a recess, wherein the first polysilicon layer is completed removed from the recess. The method further includes implanting dopants into the substrate to define an implant region. The method further includes depositing a contact etch stop layer (CESL) in the recess, wherein the CESL covers the implant region. The method further includes patterning the CESL to define a CESL block. The method further includes forming a waveguide and a grating in the substrate. The method further includes forming an interconnect structure over the waveguide, the grating and the CESL block. The method further includes etching the interconnect structure to define a cavity aligned with the grating.Type: GrantFiled: August 10, 2023Date of Patent: July 30, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Hao Huang, Hau-Yan Lu, Sui-Ying Hsu, Yuehying Lee, Chien-Ying Wu, Chien-Chang Lee, Chia-Ping Lai
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Publication number: 20240201458Abstract: An optical integrated circuit (IC) structure includes: a substrate including a fiber slot formed in an upper surface of the substrate and extending from an edge of the substrate, and an undercut formed in the upper surface and extending from the fiber slot; a semiconductor layer disposed on the substrate; a dielectric structure disposed on the semiconductor layer; an interconnect structure disposed in the dielectric structure; a plurality of vents that extend through a coupling region of the dielectric structure and expose the undercut; a fiber cavity that extends through the coupling region of dielectric structure and exposes the fiber slot; and a barrier ring disposed in the dielectric structure, the barrier ring surrounding the interconnect structure and routed around the perimeter of the coupling region.Type: ApplicationFiled: February 27, 2024Publication date: June 20, 2024Inventors: Chen-Hao Huang, Sui-Ying Hsu, YuehYing Lee, Chia-Ping Lai, Chien-Ying Wu, Hau-Yan Lu
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Patent number: 11940659Abstract: An optical integrated circuit (IC) structure includes: a substrate including a fiber slot formed in an upper surface of the substrate and extending from an edge of the substrate, and an undercut formed in the upper surface and extending from the fiber slot; a semiconductor layer disposed on the substrate; a dielectric structure disposed on the semiconductor layer; an interconnect structure disposed in the dielectric structure; a plurality of vents that extend through a coupling region of the dielectric structure and expose the undercut; a fiber cavity that extends through the coupling region of dielectric structure and exposes the fiber slot; and a barrier ring disposed in the dielectric structure, the barrier ring surrounding the interconnect structure and routed around the perimeter of the coupling region.Type: GrantFiled: August 30, 2021Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chen-Hao Huang, Hau-Yan Lu, Sui-Ying Hsu, Yuehying Lee, Chien-Ying Wu, Chia-Ping Lai
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Patent number: 11892678Abstract: A photonic device includes a silicon layer, wherein the silicon layer extends from a waveguide region of the photonic device to a device region of the photonic device, and the silicon layer includes a waveguide portion in the waveguide region. The photonic device further includes a cladding layer over the waveguide portion, wherein the device region is free of the cladding layer. The photonic device further includes a low refractive index layer in direct contact with the cladding layer, wherein the low refractive index layer comprises silicon oxide, silicon carbide, silicon oxynitride, silicon carbon oxynitride, aluminum oxide or hafnium oxide. The photonic device further includes an interconnect structure over the low refractive index layer.Type: GrantFiled: August 26, 2021Date of Patent: February 6, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chien-Ying Wu, Yuehying Lee, Sui-Ying Hsu, Chen-Hao Huang, Chien-Chang Lee, Chia-Ping Lai
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Patent number: 11892681Abstract: A coupling system includes an optical fiber configured to carry an optical signal. The coupling system further includes a chip in optical communication with the optical fiber. The chip includes a substrate. The chip further includes a grating on a first side of the substrate, wherein the grating is configured to receive the optical signal. The chip further includes an interconnect structure over the grating on the first side of the substrate, wherein the interconnect structure defines a cavity aligned with the grating. The chip further includes a first polysilicon layer on a second side of the substrate, wherein the second side of the substrate is opposite to the first side of the substrate.Type: GrantFiled: August 27, 2021Date of Patent: February 6, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Hao Huang, Hau-Yan Lu, Sui-Ying Hsu, Yuehying Lee, Chien-Ying Wu, Chien-Chang Lee, Chia-Ping Lai
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Patent number: 11848390Abstract: At least one doped silicon region is formed in a silicon layer of a semiconductor substrate, and a silicon oxide layer is formed over the silicon layer. A germanium-containing material portion is formed in the semiconductor substrate to provide a p-n junction or a p-i-n junction including the germanium-containing material portion and one of the at least one doped silicon region. A capping material layer that is free of germanium is formed over the germanium-containing material portion. A first dielectric material layer is formed over the silicon oxide layer and the capping material layer. The first dielectric material layer includes a mesa region that is raised from the germanium-containing material portion by a thickness of the capping material layer. The capping material layer may be a silicon capping layer, or may be subsequently removed to form a cavity. Dark current is reduced for the germanium-containing material portion.Type: GrantFiled: June 30, 2022Date of Patent: December 19, 2023Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chen-Hao Huang, Hau-Yan Lu, Sui-Ying Hsu, YuehYing Lee, Chien-Ying Wu, Chia-Ping Lai
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Publication number: 20230384527Abstract: A method of making a photonic device includes depositing a cladding layer over a silicon layer. The method further includes patterning the cladding layer to expose a first portion of the silicon layer, wherein a second portion of the silicon layer is covered by the patterned cladding layer, and a waveguide portion is in the second portion of the silicon layer. The method further includes depositing a low refractive index layer directly over the patterned cladding layer, wherein a refractive index of the low refractive index layer is less than a refractive index of silicon nitride.Type: ApplicationFiled: August 10, 2023Publication date: November 30, 2023Inventors: Chien-Ying WU, Yuehying LEE, Sui-Ying HSU, Chen-Hao HUANG, Chien-Chang LEE, Chia-Ping LAI
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Publication number: 20230384528Abstract: A method of using a coupling system includes aligning an optical fiber with a cavity in a chip, wherein aligning the optical fiber comprises orienting the fiber within an angle ranging from about 88-degrees to about 92-degrees with respect to a top surface of the chip. The method further includes emitting an optical signal from the optical fiber. The method further includes redirecting the optical signal into a waveguide using a grating positioned on an opposite side of the cavity from the optical fiber.Type: ApplicationFiled: August 10, 2023Publication date: November 30, 2023Inventors: Sui-Ying HSU, Yuehying LEE, Chien-Ying WU, Chen-Hao HUANG, Chien-Chang LEE, Chia-Ping LAI
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Publication number: 20230384526Abstract: A method of making a chip includes depositing a first polysilicon layer on a top surface and a bottom surface of a substrate. The method further includes patterning the first polysilicon layer to define a recess, wherein the first polysilicon layer is completed removed from the recess. The method further includes implanting dopants into the substrate to define an implant region. The method further includes depositing a contact etch stop layer (CESL) in the recess, wherein the CESL covers the implant region. The method further includes patterning the CESL to define a CESL block. The method further includes forming a waveguide and a grating in the substrate. The method further includes forming an interconnect structure over the waveguide, the grating and the CESL block. The method further includes etching the interconnect structure to define a cavity aligned with the grating.Type: ApplicationFiled: August 10, 2023Publication date: November 30, 2023Inventors: Chen-Hao HUANG, Hau-Yan LU, Sui-Ying HSU, Yuehying LEE, Chien-Ying WU, Chien-Chang LEE, Chia-Ping LAI
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Publication number: 20230358959Abstract: A photonic device includes an optical coupler, a photodetector, a waveguide structure, a metal-dielectric stack, a contact, an interlayer dielectric layer, and a protection layer. The optical coupler, the photodetector, and the waveguide structure are over a substrate. The waveguide structure is laterally connected to the optical couple. A top of the waveguide structure is lower than a top of the optical coupler. The metal-dielectric stack is over the optical coupler, the photodetector, and the waveguide structure. The metal-dielectric stack has a hole above the optical coupler. The contact connects the photodetector to the metal-dielectric stack. The interlayer dielectric layer is below the metal-dielectric stack and surrounds the contact. The protection layer lines the hole of the metal-dielectric stack. A bottom surface of the protection layer is lower than a top surface of the contact.Type: ApplicationFiled: July 14, 2023Publication date: November 9, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Sui-Ying HSU, Yueh-Ying LEE, Chien-Ying WU, Chen-Hao HUANG, Chien-Chang LEE, Chia-Ping LAI
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Patent number: 11740409Abstract: A photonic device includes an optical coupler, a waveguide structure, a metal-dielectric stack, and a protection layer. The optical coupler is over a semiconductor substrate. The waveguide structure is over the semiconductor substrate and laterally connected to the optical coupler. A top of the waveguide structure is lower than a top of the optical coupler. The metal-dielectric stack is over the optical coupler and the waveguide structure. The metal-dielectric stack has a hole above the optical coupler. The protection layer lines the hole of the metal-dielectric stack.Type: GrantFiled: May 9, 2022Date of Patent: August 29, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Sui-Ying Hsu, Yueh-Ying Lee, Chien-Ying Wu, Chen-Hao Huang, Chien-Chang Lee, Chia-Ping Lai
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Publication number: 20230064550Abstract: A coupling system includes an optical fiber configured to carry an optical signal. The coupling system further includes a chip in optical communication with the optical fiber. An angle between the optical fiber and a top surface of the chip ranges from about 92-degrees to about 88-degrees. The chip includes a grating configured to receive the optical signal; and a waveguide, wherein the grating is configured to receive the optical signal and redirect the optical signal along the waveguide. ms.Type: ApplicationFiled: August 27, 2021Publication date: March 2, 2023Inventors: Sui-Ying HSU, Yuehying LEE, Chien-Ying WU, Chen-Hao HUANG, Chien-Chang LEE, Chia-Ping LAI
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Publication number: 20230069212Abstract: An optical integrated circuit (IC) structure includes: a substrate including a fiber slot formed in an upper surface of the substrate and extending from an edge of the substrate, and an undercut formed in the upper surface and extending from the fiber slot; a semiconductor layer disposed on the substrate; a dielectric structure disposed on the semiconductor layer; an interconnect structure disposed in the dielectric structure; a plurality of vents that extend through a coupling region of the dielectric structure and expose the undercut; a fiber cavity that extends through the coupling region of dielectric structure and exposes the fiber slot; and a barrier ring disposed in the dielectric structure, the barrier ring surrounding the interconnect structure and routed around the perimeter of the coupling region.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Inventors: Chen-Hao HUANG, Hau-Yan Lu, Sui-Ying Hsu, Yuehying Lee, Chien-Ying Wu, Chia-Ping Lai
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Publication number: 20230068603Abstract: A photonic device includes a silicon layer, wherein the silicon layer extends from a waveguide region of the photonic device to a device region of the photonic device, and the silicon layer includes a waveguide portion in the waveguide region. The photonic device further includes a cladding layer over the waveguide portion, wherein the device region is free of the cladding layer. The photonic device further includes a low refractive index layer in direct contact with the cladding layer, wherein the low refractive index layer comprises silicon oxide, silicon carbide, silicon oxynitride, silicon carbon oxynitride, aluminum oxide or hafnium oxide. The photonic device further includes an interconnect structure over the low refractive index layer.Type: ApplicationFiled: August 26, 2021Publication date: March 2, 2023Inventors: Chien-Ying WU, Yuehying LEE, Sui-Ying HSU, Chen-Hao HUANG, Chien-Chang LEE, Chia-Ping LAI
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Publication number: 20230061940Abstract: A coupling system includes an optical fiber configured to carry an optical signal. The coupling system further includes a chip in optical communication with the optical fiber. The chip includes a substrate. The chip further includes a grating on a first side of the substrate, wherein the grating is configured to receive the optical signal. The chip further includes an interconnect structure over the grating on the first side of the substrate, wherein the interconnect structure defines a cavity aligned with the grating. The chip further includes a first polysilicon layer on a second side of the substrate, wherein the second side of the substrate is opposite to the first side of the substrate.Type: ApplicationFiled: August 27, 2021Publication date: March 2, 2023Inventors: Chen-Hao HUANG, Hau-Yan LU, Sui-Ying HSU, Yuehying LEE, Chien-Ying WU, Chien-Chang LEE, Chia-Ping LAI