Patents by Inventor Chien-Ying WU
Chien-Ying WU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220336684Abstract: At least one doped silicon region is formed in a silicon layer of a semiconductor substrate, and a silicon oxide layer is formed over the silicon layer. A germanium-containing material portion is formed in the semiconductor substrate to provide a p-n junction or a p-i-n junction including the germanium-containing material portion and one of the at least one doped silicon region. A capping material layer that is free of germanium is formed over the germanium-containing material portion. A first dielectric material layer is formed over the silicon oxide layer and the capping material layer. The first dielectric material layer includes a mesa region that is raised from the germanium-containing material portion by a thickness of the capping material layer. The capping material layer may be a silicon capping layer, or may be subsequently removed to form a cavity. Dark current is reduced for the germanium-containing material portion.Type: ApplicationFiled: June 30, 2022Publication date: October 20, 2022Inventors: Chen-Hao HUANG, Hau-Yan LU, Sui-Ying HSU, YuehYing LEE, Chien-Ying WU, Chia-Ping LAI
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Patent number: 11476288Abstract: A method includes epitaxially growing a first III-V compound layer over a semiconductive substrate. A second III-V compound layer is epitaxially grown over the first III-V compound layer. A source/drain contact is formed over the second III-V compound layer. A gate structure is formed over the second III-V compound layer. A pattern is formed shielding the gate structure and the source/drain contact, in which a portion of the second III-V compound layer is free from coverage by the pattern.Type: GrantFiled: October 21, 2019Date of Patent: October 18, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chien-Ying Wu, Li-Hsin Chu, Chung-Chuan Tseng, Chia-Wei Liu
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Patent number: 11442230Abstract: An optical structure may be provided by forming a silicon grating structure over a dielectric material layer, depositing at least one dielectric material layer over the silicon grating structure, and depositing at least one dielectric etch stop layer over the at least one dielectric material layer. The at least one dielectric etch stop layer includes at least one dielectric material selected from silicon nitride and silicon oxynitride. A passivation dielectric layer may be formed over the at least one dielectric etch stop layer, and a patterned etch mask layer may be formed over the passivation dielectric layer. An opening may be formed through an unmasked portion of the passivation dielectric layer by performing an anisotropic etch process that etches the dielectric material selective to a silicon nitride or silicon oxynitride using the patterned etch mask layer as a masking structure. The at least one etch mask layer minimizes overetching.Type: GrantFiled: November 13, 2020Date of Patent: September 13, 2022Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Yueh Ying Lee, Chien-Ying Wu, Sui-Ying Hsu, Chen-Hao Huang, Chien-Chang Lee, Chia-Ping Lai
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Publication number: 20220269003Abstract: A photonic device includes an optical coupler, a waveguide structure, a metal-dielectric stack, and a protection layer. The optical coupler is over a semiconductor substrate. The waveguide structure is over the semiconductor substrate and laterally connected to the optical coupler. A top of the waveguide structure is lower than a top of the optical coupler. The metal-dielectric stack is over the optical coupler and the waveguide structure. The metal-dielectric stack has a hole above the optical coupler. The protection layer lines the hole of the metal-dielectric stack.Type: ApplicationFiled: May 9, 2022Publication date: August 25, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Sui-Ying HSU, Yueh-Ying LEE, Chien-Ying WU, Chen-Hao HUANG, Chien-Chang LEE, Chia-Ping LAI
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Publication number: 20220238730Abstract: At least one doped silicon region is formed in a silicon layer of a semiconductor substrate, and a silicon oxide layer is formed over the silicon layer. A germanium-containing material portion is formed in the semiconductor substrate to provide a p-n junction or a p-i-n junction including the germanium-containing material portion and one of the at least one doped silicon region. A capping material layer that is free of germanium is formed over the germanium-containing material portion. A first dielectric material layer is formed over the silicon oxide layer and the capping material layer. The first dielectric material layer includes a mesa region that is raised from the germanium-containing material portion by a thickness of the capping material layer. The capping material layer may be a silicon capping layer, or may be subsequently removed to form a cavity. Dark current is reduced for the germanium-containing material portion.Type: ApplicationFiled: January 27, 2021Publication date: July 28, 2022Inventors: Chen-Hao HUANG, Hau-Yan LU, Sui-Ying HSU, Yueh Ying LEE, Chien-Ying WU, Chia-Ping LAI
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Publication number: 20220155527Abstract: An optical structure may be provided by forming a silicon grating structure over a dielectric material layer, depositing at least one dielectric material layer over the silicon grating structure, and depositing at least one dielectric etch stop layer over the at least one dielectric material layer. The at least one dielectric etch stop layer includes at least one dielectric material selected from silicon nitride and silicon oxynitride. A passivation dielectric layer may be formed over the at least one dielectric etch stop layer, and a patterned etch mask layer may be formed over the passivation dielectric layer. An opening may be formed through an unmasked portion of the passivation dielectric layer by performing an anisotropic etch process that etches the dielectric material selective to a silicon nitride or silicon oxynitride using the patterned etch mask layer as a masking structure. The at least one etch mask layer minimizes overetching.Type: ApplicationFiled: November 13, 2020Publication date: May 19, 2022Inventors: Yueh Ying LEE, Chien-Ying WU, Sui-Ying HSU, Chen-Hao HUANG, Chien-Chang LEE, Chia-Ping LAI
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Patent number: 11327228Abstract: A method for fabricating a photonic device is provided. The method includes forming an optical coupler and a waveguide structure connected to the optical coupler over a semiconductor substrate; forming a metal-dielectric stack over the optical coupler and the waveguide structure; etching a hole in the metal-dielectric stack and vertically overlapping the optical coupler; and forming a protection layer on a sidewall and a bottom of the hole.Type: GrantFiled: July 9, 2020Date of Patent: May 10, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Sui-Ying Hsu, Yueh-Ying Lee, Chien-Ying Wu, Chen-Hao Huang, Chien-Chang Lee, Chia-Ping Lai
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Publication number: 20220011511Abstract: A method for fabricating a photonic device is provided. The method includes forming an optical coupler and a waveguide structure connected to the optical coupler over a semiconductor substrate; forming a metal-dielectric stack over the optical coupler and the waveguide structure; etching a hole in the metal-dielectric stack and vertically overlapping the optical coupler; and forming a protection layer on a sidewall and a bottom of the hole.Type: ApplicationFiled: July 9, 2020Publication date: January 13, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Sui-Ying HSU, Yueh-Ying LEE, Chien-Ying WU, Chen-Hao HUANG, Chien-Chang LEE, Chia-Ping LAI
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Patent number: 11175452Abstract: A method for fabricating a photonic device is provided. The method includes patterning a semiconductor layer to form a waveguide structure, a semiconductor structure connected to the waveguide structure, and a dummy semiconductor structure disconnected from the waveguide structure and the semiconductor structure; epitaxially growing an epitaxial semiconductor feature over the semiconductor structure and a dummy epitaxial semiconductor feature over the dummy semiconductor structure; depositing a first capping film over the epitaxial semiconductor feature and the dummy epitaxial semiconductor feature; depositing a second capping film over the first capping film, wherein an oxide concentration of the second capping film is greater than an oxide concentration of the first capping film; and patterning the first and second capping films to form at least a dummy composite capping layer over the dummy epitaxial semiconductor feature.Type: GrantFiled: August 11, 2020Date of Patent: November 16, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Sui-Ying Hsu, Yueh-Ying Lee, Chien-Ying Wu, Chen-Hao Huang, Chien-Chang Lee, Chia-Ping Lai
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Publication number: 20200052018Abstract: A method includes epitaxially growing a first III-V compound layer over a semiconductive substrate. A second III-V compound layer is epitaxially grown over the first III-V compound layer. A source/drain contact is formed over the second III-V compound layer. A gate structure is formed over the second III-V compound layer. A pattern is formed shielding the gate structure and the source/drain contact, in which a portion of the second III-V compound layer is free from coverage by the pattern.Type: ApplicationFiled: October 21, 2019Publication date: February 13, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chien-Ying WU, Li-Hsin CHU, Chung-Chuan TSENG, Chia-Wei LIU
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Patent number: 10453881Abstract: An infrared image sensor component includes a semiconductor substrate, an active pixel region disposed on the semiconductor substrate for receiving an infrared ray, and a transistor coupled to the active pixel region. The transistor includes a gate and a source/drain stressor disposed adjacent to the gate. The active pixel region includes a III-V compound material.Type: GrantFiled: January 13, 2018Date of Patent: October 22, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chien-Ying Wu, Li-Hsin Chu, Chung-Chuan Tseng, Chia-Wei Liu
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Patent number: 10050103Abstract: A method of making a metal insulator metal (MIM) capacitor includes forming a copper bulk layer in a base layer, wherein the copper bulk layer includes a hillock extending from a top surface thereof. The method further includes depositing an etch stop layer over the base layer and the copper bulk layer. The method further includes depositing an oxide-based dielectric layer over the etch stop layer. The method further includes forming a capacitor over the oxide-based dielectric layer. The method further includes forming a contact extending through the oxide-based dielectric layer and the etch stop layer to contact the copper bulk layer, wherein the forming of the contact removes the hillock.Type: GrantFiled: May 25, 2017Date of Patent: August 14, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Fang-Ting Kuo, Ren-Wei Xiao, Sheng Yu Lin, Chia-Wei Liu, Chun Hua Chang, Chien-Ying Wu
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Publication number: 20180138220Abstract: An infrared image sensor component includes a semiconductor substrate, an active pixel region disposed on the semiconductor substrate for receiving an infrared ray, and a transistor coupled to the active pixel region. The transistor includes a gate and a source/drain stressor disposed adjacent to the gate. The active pixel region includes a III-V compound material.Type: ApplicationFiled: January 13, 2018Publication date: May 17, 2018Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chien-Ying WU, Li-Hsin CHU, Chung-Chuan TSENG, Chia-Wei LIU
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Patent number: 9871067Abstract: An infrared image sensor component includes at least one III-V compound layer on the semiconductor substrate, in which the portion of the III-V compound layer(s) uncovered by the patterns is utilized as active pixel region for detecting the incident infrared ray. The infrared image sensor component includes at least one transistor coupled to the active pixel region, and charge generated by the active pixel region is transmitted to the transistor.Type: GrantFiled: February 23, 2016Date of Patent: January 16, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chien-Ying Wu, Li-Hsin Chu, Chung-Chuan Tseng, Chia-Wei Liu
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Publication number: 20170263694Abstract: A method of making a metal insulator metal (MIM) capacitor includes forming a copper bulk layer in a base layer, wherein the copper bulk layer includes a hillock extending from a top surface thereof. The method further includes depositing an etch stop layer over the base layer and the copper bulk layer. The method further includes depositing an oxide-based dielectric layer over the etch stop layer. The method further includes forming a capacitor over the oxide-based dielectric layer. The method further includes forming a contact extending through the oxide-based dielectric layer and the etch stop layer to contact the copper bulk layer, wherein the forming of the contact removes the hillock.Type: ApplicationFiled: May 25, 2017Publication date: September 14, 2017Inventors: Fang-Ting KUO, Ren-Wei XIAO, Sheng Yu LIN, Chia-Wei LIU, Chun Hua CHANG, Chien-Ying WU
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Patent number: 9666660Abstract: A metal insulator metal (MIM) capacitor includes a base layer and a copper bulk layer in the base layer. The MIM capacitor further includes an etch stop layer over the base layer and the copper bulk layer and an oxide-based dielectric layer over the etch stop layer. The MIM capacitor further includes a capacitor bottom layer over the oxide-based dielectric layer, an insulator layer over the capacitor bottom layer, and a capacitor top layer over the insulator layer.Type: GrantFiled: August 16, 2013Date of Patent: May 30, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Fang-Ting Kuo, Ren-Wei Xiao, Sheng Yu Lin, Chia-Wei Liu, Chun Hua Chang, Chien-Ying Wu
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Publication number: 20170141148Abstract: An infrared image sensor component includes at least one III-V compound layer on the semiconductor substrate, in which the portion of the III-V compound layer(s) uncovered by the patterns is utilized as active pixel region for detecting the incident infrared ray. The infrared image sensor component includes at least one transistor coupled to the active pixel region, and charge generated by the active pixel region is transmitted to the transistor.Type: ApplicationFiled: February 23, 2016Publication date: May 18, 2017Inventors: Chien-Ying WU, Li-Hsin CHU, Chung-Chuan TSENG, Chia-Wei LIU
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Publication number: 20150048483Abstract: A metal insulator metal (MIM) capacitor includes a base layer and a copper bulk layer in the base layer. The MIM capacitor further includes an etch stop layer over the base layer and the copper bulk layer and an oxide-based dielectric layer over the etch stop layer. The MIM capacitor further includes a capacitor bottom layer over the oxide-based dielectric layer, an insulator layer over the capacitor bottom layer, and a capacitor top layer over the insulator layer.Type: ApplicationFiled: August 16, 2013Publication date: February 19, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Fang-Ting KUO, Ren-Wei XIAO, Sheng Yu LIN, Chia-Wei LIU, Chun Hua CHANG, Chien-Ying WU