Abstract: An image processing device includes a three-dimensional noise reduction (3D NR) circuit, an artificial intelligence noise reduction (AI NR) circuit, a weight determination circuit and an image blending circuit. The 3D NR circuit performs a 3D NR operation on input image data to generate first image data. The AI NR circuit performs an AI NR operation on the input image data to generate second image data. The weight determination circuit outputs a blending weight according to a motion index. The image blending circuit blends the first image data and the second image data according to the blending weight to generate output image data.

Abstract: A hub structure having an anti-lock braking system contains: a hub assembly and an anti-locking assembly. The hub assembly is located on a center of a wheel and includes a holder and a connection shaft. The anti-locking assembly is received in the holder and is fitted on the connection shaft, and the anti-locking assembly includes an anti-lock seat received in the holder and fitted on the connection shaft to rotate with the holder simultaneously, multiple eddy current elements arranged on two sides of the anti-lock seat and two ends of the connection shaft. A predetermined distance is defined between any two adjacent eddy current elements, and a respective eddy current element has at least one electromagnetic induction portion, when two corresponding electromagnetic induction portions are electrically conducted, a current magnetic field produces so that the anti-lock seat produces reverse currents to stop rotation.

Abstract: A method, a network device, and a non-transitory computer-readable storage medium are described in relation to a low latency, low loss, and scalable throughput (LI4S)-triggered prioritized connection service. The LI4S-triggered prioritized connection service may enable an evolved packet data gateway (ePDG) to provision prioritized and non-prioritized tunnels with end devices via untrusted wireless local area networks. The prioritized tunnel may support LI4S or another quality of service in which the ePDG may provide prioritized data forwarding. The end device may transmit a request that includes priority data.

Abstract: Synthetic endornaviral satellite RNA molecules and satellite particles containing the same are disclosed. The synthetic endornaviral satellite RNA molecules can include coding and/or non-coding cargo sequences, and are heritable through generations of plants. Also disclosed are methods of using the endornaviral satellite RNA molecules and satellite particles containing the same to change plant phenotypes, improve plant stress resistance, and improve plant pest and pathogen resistance.

Abstract: A semiconductor structure includes a circuit substrate, a semiconductor die, and a cover. The semiconductor die is disposed on the circuit substrate. The cover is disposed over the semiconductor die and over the circuit substrate. The cover comprises a lid portion and a support portion. The structure includes a first adhesive bonding the support portion to the circuit substrate and a second adhesive bonding the support portion and the lid portion.

Abstract: An integrated circuit (IC) structure includes a first transistor and a second transistor. The first transistor includes a first active region and a first gate disposed on the first active region, in which the first gate has a first effective gate length along a first direction parallel to a lengthwise direction of the first active region. The second transistor includes a second active region and a second gate disposed on the second active region, and includes a plurality of gate structures arranged along the first direction and separated from each other, in which the second gate has a second effective gate length along the first direction, the second effective gate length is n times the first effective gate length, and n is a positive integer greater than 1.

Abstract: A method for forming an optical device structure is provided. The method includes disposing a first end portion of an optical fiber into a fiber array unit structure. The first end portion penetrates through the fiber array unit structure. The method includes bonding the first end portion of the optical fiber to a co-packaged optical device. The method includes bonding a fiber shield structure to the fiber array unit structure and the co-packaged optical device after the first end portion is bonded to the co-packaged optical device. The fiber shield structure surrounds the optical fiber.

Abstract: A sensor package structure is provided. The sensor package structure includes a substrate, a sensor chip, a ring-shaped wall, and a light-permeable layer. The substrate has a first surface and a second surface that is opposite to the first surface. The first surface of the substrate has a chip-bonding region and a connection region that surrounds the chip-bonding region, and the substrate has a plurality of protrusions arranged in the connection region. The sensor chip is disposed on the chip-bonding region of the substrate and is electrically coupled to the substrate. The ring-shaped wall is formed on the connection region of the substrate, and the protrusions of the substrate are embedded in and gaplessly connected to the ring-shaped wall. The light-permeable layer is disposed on the ring-shaped wall, and the light-permeable layer, the ring-shaped wall, and the substrate jointly define an enclosed space therein.

Abstract: A computing system performs shared cache allocation to allocate cache resources to groups of tasks. The computing system monitors the bandwidth at a memory hierarchy device that is at a next level to the cache in a memory hierarchy of the computing system. The computing system estimates a change in dynamic power from a corresponding change in the bandwidth before and after the cache resources are allocated. The allocation of the cache resources are adjusted according to an allocation policy that receives inputs including the estimated change in the dynamic power and a performance indication of task execution.

Abstract: A method may include establishing, for a user equipment (UE) device, a data session via a network and determining whether the network is congested or overloaded. The method may also include instructing the UE device to re-register for a Category M1 (Cat-M1) data session, in response to determining that the network is congested or overloaded.

Abstract: The present utility invention provides a food mixture forming apparatus, which comprises a forming assembly and a demolding assembly. The forming assembly comprises a first slider and a second slider. First, the first slider and the second slider move along a first direction to shape a food mixture, then, the demolding assembly moves along a second direction to finish the forming process.

Abstract: Systems and methods described herein enable 5G core session management function (SMF)/user plan function (UPF) relocation to support ATSSS-enabled evolved packet data gateways (ePDG). An ePDG receives an access traffic steering, switching and splitting (ATSSS) trigger message from a user equipment (UE) device. The UE device is connected via a first session using a session management function (SMF) and a via a second session using a packet data network gateway (PGW). The ATSSS trigger message includes an SMF identifier for the SMF. The ePDG sends, in response to the ATSSS trigger message, a request to the SMF to merge the first session and the second session into a single registration.

Abstract: A sensor lens assembly having a non-soldering configuration is provided. The sensor lens assembly includes a circuit board, an optical module fixed on the circuit board, a sensor chip assembled to the circuit board, a plurality of wires electrically coupled to the sensor chip and the circuit board, and a cover that overcovers the sensor chip and the wires. The cover includes a light-permeable sheet and an opaque frame. The light-permeable sheet has a ring-shaped notch recessed in an edge of an inner surface thereof. The opaque frame is formed on the ring-shaped notch and is disposed on the circuit board, the light-permeable sheet and the sensor chip are spaced apart from each other, and the sensor chip and the wires are arranged in a space that is defined by the light-permeable sheet and the opaque frame.

Abstract: Synthetic endornaviral satellite RNA molecules and satellite particles containing the same are disclosed. The synthetic endornaviral satellite RNA molecules can include coding and/or non-coding cargo sequences, and are heritable through generations of plants. Also disclosed are methods of using the endornaviral satellite RNA molecules and satellite particles containing the same to change plant phenotypes, improve plant stress resistance, and improve plant pest and pathogen resistance.

Abstract: A semiconductor structure includes a circuit substrate, a semiconductor die, and a cover. The semiconductor die is disposed on the circuit substrate. The cover is disposed over the semiconductor die and over the circuit substrate. The cover comprises a lid portion and a support portion. The structure includes a first adhesive bonding the support portion to the circuit substrate and a second adhesive bonding the support portion and the lid portion.

Abstract: The present disclosure provides a memory device, including a memory array, a tracking circuit, a memory controller, and a word line driver. A plurality of word lines are in communication with a plurality of memory cells of the memory array. The memory controller decodes a memory address of a memory access command to generate a decoded row address signal. The word line driver is configured to assert one of the plurality of word lines in response to the decoded row address signal. In response to detecting a switching event of a clock control signal derived from an input clock signal of the memory device, the memory controller asserts an tracking acceleration signal obtained from a tracking word line of the memory device to activate one or more first tracking arrays of the plurality of tracking arrays to pull down a voltage level of a tracking bit line.

Abstract: A memory device and a method of operating the memory device are disclosed. In one aspect, the memory device includes a bit line connected to a plurality of memory cells of a memory array, the bit line having a first length. The memory device includes a first programmable bit line having a second length determined based on a size of the memory array, and a charge sharing circuit connected to the bit line and the first programmable bit line. The charge sharing circuit is configured to transfer a charge from the bit line to the first programmable bit line. The memory device includes a discharge circuit connected to the first programmable bit line, the discharge circuit configured to discharge a stored charge in the first programmable bit line.

Abstract: A semiconductor device and related method for forming a gate structure. In some embodiments, a semiconductor device includes a fin extending from a substrate. In some cases, the fin includes a plurality of semiconductor channel layers. In some examples, the semiconductor device further includes a gate dielectric surrounding each of the plurality of semiconductor channel layers. In some embodiments, a first thickness of the gate dielectric disposed on a top surface of a topmost semiconductor channel layer of the plurality of semiconductor channel layers is greater than a second thickness of the gate dielectric disposed on a surface of another semiconductor channel layer disposed beneath the topmost semiconductor channel layer.

Abstract: An integrated circuit package includes first and second dies bonded to each other. The first die includes first die pads over a first device, first bonding pads over the first die pads, a first conductive via disposed between and electrically connected to a first one of the first die pads and a first one of the first bonding pads, and a first thermal via disposed between a second one of the first die pads and a second one of the first bonding pads and electrically insulated from the second one of the first die pads or the second one of the first bonding pads. The second die includes second bonding pads. The first one of the first bonding pads is connected to a first one of the second bonding pads. The second one of the first bonding pads is connected to a second one of the second bonding pads.

Abstract: A method includes providing a substrate, a dummy fin, and a stack of semiconductor channel layers; forming an interfacial layer wrapping around each of the semiconductor channel layers; depositing a high-k dielectric layer, wherein a first portion of the high-k dielectric layer over the interfacial layer is spaced away from a second portion of the high-k dielectric layer on sidewalls of the dummy fin by a first distance; depositing a first dielectric layer over the dummy fin and over the semiconductor channel layers, wherein a merge-critical-dimension of the first dielectric layer is greater than the first distance thereby causing the first dielectric layer to be deposited in a space between the dummy fin and a topmost layer of the stack of semiconductor channel layers, thereby providing air gaps between adjacent layers of the stack of semiconductor channel layers and between the dummy fin and the stack of semiconductor channel layers.