Patents by Inventor Chien Chih Chiu
Chien Chih Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240148301Abstract: The present invention provides a smart wearable device, which is held on an upper body of a wearer by a plurality of contact pad sets, and has a connection unit, a first sensing module, a second sensing module, and an extension unit.Type: ApplicationFiled: November 7, 2022Publication date: May 9, 2024Inventors: Chien-Hsiang Chang, Yang-Cheng Lin, Wei-Chih Lien, Tseng-Ping Chiu, Pei-Yun Wu, Bo Liu
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Publication number: 20240154630Abstract: A communication device is adapted to be coupled to an external antenna configured to receive a wireless signal in a frequency band. The communication device includes a connector, an internal antenna, a switch, a wireless communication module, and a controller. The connector is adapted to be coupled to the external antenna. The internal antenna is configured to receive the wireless signal in the frequency band. The switch is selectively coupled to the connector or the internal antenna. The wireless communication module is coupled to the switch, and is configured to generate a signal strength indicator parameter based on the wireless signal in the frequency band. The controller is configured to control switching of the switch based on the signal strength indicator parameter.Type: ApplicationFiled: April 11, 2023Publication date: May 9, 2024Applicant: MITAC COMPUTING TECHNOLOGY CORPORATIONInventor: Chien-Chih CHIU
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Patent number: 11969727Abstract: Present invention is related to a tumor microenvironment on chip or a biochip for cell therapy having a carrier, a first cell or tissue culture area and a second cell or tissue area imbedded within the carrier. The present invention provides a biochip successfully cooperating micro fluidic technology and cell culture achieving the goal for detecting or testing the function of cell therapy for cancer or tumor.Type: GrantFiled: October 22, 2021Date of Patent: April 30, 2024Assignees: China Medical University, China Medical University HospitalInventors: Yi-Wen Chen, Ming-You Shie, Der-Yang Cho, Shao-Chih Chiu, Kai-Wen Kan, Chien-Chang Chen
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Patent number: 11930573Abstract: A power supply device is provided. The power supply device includes a power converter and a controller. The controller controls the power converter to generate an output power. The controller includes a first detection circuit and a second detection circuit. The first detection circuit detects the output power to obtain a first detection result. The first detection result is a variation of an output current value of the output power. The second detection circuit detects electrical characteristics other than the output current value to obtain a second detection result. The controller determines whether to limit output of the output power according to a relationship between the first detection result and the second detection result.Type: GrantFiled: October 5, 2022Date of Patent: March 12, 2024Assignee: Power Forest Technology CorporationInventors: Rong-Jie Tu, Hung-Chih Chiu, Chien-Lung Lee
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Publication number: 20230411144Abstract: A method for forming a semiconductor device includes followings. A metal layer is formed to embedded in a first dielectric layer. An etch stop layer is formed over the metal layer and the first dielectric layer. A second dielectric layer is formed over the etch stop layer. A portion of the second dielectric layer is removed to expose a portion of the etch stop layer and to form a via by a dry etching process. The portion of the etch stop layer exposed by the second dielectric layer is removed to expose the metal layer and to form a damascene cavity by a wet etching process. A damascene structure is formed in the damascene cavity.Type: ApplicationFiled: June 16, 2022Publication date: December 21, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Han Chen, Hung-Chun Chen, Yuan-Chun Chien, Wei Tse Hsu, Yu-Yu Chen, Chien-Chih Chiu
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Publication number: 20230377956Abstract: A method of forming a semiconductor device structure is disclosed. First and second etch stop layers are formed overlying a semiconductor structure having a conductive feature formed therein. A dielectric layer is formed overlying the second etch stop layer, and a hard mask, that comprises a tungsten-based material, is formed overlying the dielectric layer, and patterned. A resist layer is formed over the patterned hard mask. Using the patterned resist layer as a mask, a first etching process is performed to form a via opening that extends partially through the dielectric layer. Using the patterned hard mask as an etch mask, a second etching process (e.g., dry etching process) is performed to extend the via opening through the second etch stop layer, and a third etching process (e.g., wet etching process) is performed to extend the via opening through the first etch stop layer to reach the conductive feature.Type: ApplicationFiled: May 23, 2022Publication date: November 23, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Han Chen, Shih-Yu Chang, Chien-Chih Chiu, Huang-Ming Chen
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Publication number: 20230262912Abstract: The present disclosure is drawn to covers for electronic devices. In one example, a cover for an electronic device can include a light metal substrate including a first surface. A first micro-arc oxidation layer may be on the first surface of the light metal substrate, the first micro-arc oxidation layer can include a cationic dye bonded to the first surface via an anionic inorganic bridging compound.Type: ApplicationFiled: July 31, 2020Publication date: August 17, 2023Applicant: Hewlett-Packard Development Company, L.P.Inventors: CHIEN-CHIH CHIU, HSIN-CHIEN CHU, KUAN-TING WU
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Publication number: 20230155001Abstract: A method includes forming a transistor comprising a source/drain region and a gate electrode, forming a source/drain contact plug over and electrically connecting to the source/drain region, forming a first inter-layer dielectric over the source/drain contact plug, forming an etch stop layer over the first inter-layer dielectric, etching the etch stop layer to form a first via opening, forming a second inter-layer dielectric over the first inter-layer dielectric, performing an etching process, so that the second inter-layer dielectric is etched to form a trench, and the first via opening in the etch stop layer is extended into the first inter-layer dielectric to reveal the source/drain contact plug, and filling the trench and the first via opening in common processes to form a metal line and a via, respectively.Type: ApplicationFiled: February 16, 2022Publication date: May 18, 2023Inventors: Chien-Han Chen, Shih-Yu Chang, Chien-Chih Chiu, Huang-Ming Chen, Jyu-Horng Shieh
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Patent number: 11615983Abstract: A semiconductor interconnect structure includes a conductive line electrically coupled to an active semiconductor device, a first etch stop layer formed over the conductive line, a first dielectric layer formed over the first etch stop layer, a second etch stop layer formed over the first dielectric layer, a second dielectric layer formed over the second etch stop layer, and an interconnect structure electrically coupled to the conductive line and extending through the first etch stop layer, the first dielectric layer, the second etch stop layer, and the second dielectric layer. The interconnect structure includes a via extending through the first etch stop layer, the second etch stop layer, and the first dielectric layer and a trench extending through the second dielectric layer.Type: GrantFiled: February 3, 2021Date of Patent: March 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Chien-Han Chen, Chien-Chih Chiu, Shih-Yu Chang, Da-Wei Lin, Y.T. Chen
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Publication number: 20230060269Abstract: A method includes forming a first conductive feature over a substrate, forming an etch-stop layer (ESL) stack over the first conductive feature, forming a first interlayer dielectric (ILD) layer over the ESL stack, forming a patterned ESL having a first opening over the first ILD layer, forming a second ILD layer over the patterned ESL, thereby filling the first opening, forming a patterned HM having a second opening over the second ILD layer, where a width of the second opening is greater than a width of the first opening, performing an etching process to form a first trench in the second ILD layer and a second trench in the first ILD layer, where the second trench exposes the first conductive feature, and subsequently depositing a conductive layer in the first trench and the second trench, thereby forming a second conductive feature interconnecting a third conductive to the first conductive feature.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Inventors: Hsiu-Wen Hsueh, Cai-Ling Wu, Chii-Ping Chen, Chien-Chih Chiu
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Publication number: 20230028904Abstract: A method includes depositing an inter-metal dielectric (IMD) layer over a conductive line. A via opening is formed in the IMD layer and directly over the conductive line. A width of the conductive line is greater than a width of the via opening. An overlay measurement is performed. The overlay measurement includes obtaining a backscattered electron image of the via opening and the conductive line and determining an overlay between the via opening and the conductive line according to the backscattered electron image.Type: ApplicationFiled: January 31, 2022Publication date: January 26, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Yu CHANG, Chien-Han CHEN, Chien-Chih CHIU, Chi-Che TSENG
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Publication number: 20220367226Abstract: Semiconductor devices, methods of manufacturing the semiconductor device and tools are disclosed herein. Some methods include providing an electrostatic chuck and placing an edge ring adjacent to the electrostatic chuck. The electrostatic chuck includes a first electrode to generate a sheath at a first distance over the electrostatic chuck. The edge ring includes a coil and a second electrode to generate an electric field control to maintain a portion of the sheath over the edge ring in a coplanar orientation with the portion of the sheath over the electrostatic chuck.Type: ApplicationFiled: November 5, 2021Publication date: November 17, 2022Inventors: Shih-Yu Chang, Chien-Han Chen, Chien-Chih Chiu, Chi-Che Tseng
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Publication number: 20220367253Abstract: A method for forming an interconnect structure is described. In some embodiments, the method includes forming a mask structure on a dielectric layer, and the mask structure includes a first layer, a second layer disposed on the first layer, and a third layer disposed on the second layer. The method further includes forming first openings having first dimensions in the first layer and forming a multilayer structure over the first layer. The multilayer structure includes a bottom layer disposed in the first openings and over the first layer, a middle layer disposed on the bottom layer, and a photoresist layer disposed on the middle layer. The method further includes forming second openings having second dimensions in the bottom layer to expose portions of the dielectric layer, and the second dimensions are smaller than the first dimensions. The method further includes extending the second openings into the dielectric layer.Type: ApplicationFiled: September 20, 2021Publication date: November 17, 2022Inventors: Chien-Han CHEN, Da-Wei LIN, Yi Tang CHEN, Chien-Chih CHIU
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Patent number: 11502001Abstract: A method of forming a semiconductor device includes forming a conductive line over a substrate; forming an etch stop layer (ESL) over the conductive line, the ESL extending continuously along an upper surface of the conductive line and along an upper surface of a first dielectric layer adjacent to the conductive line, where a first lower surface of the ESL contacts the upper surface of the conductive line, and a second lower surface of the ESL contacts the upper surface of the first dielectric layer, the first lower surface being closer to the substrate than the second lower surface; forming a second dielectric layer over the ESL; forming an opening in the second dielectric layer, the opening exposing a first portion of the ESL; removing the first portion of the ESL to expose the conductive line; and filling the opening with an electrically conductive material to form a via.Type: GrantFiled: February 13, 2019Date of Patent: November 15, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chien-Han Chen, Chien-Chih Chiu, Ming-Chung Liang
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Publication number: 20220285216Abstract: A method of forming a semiconductor device includes forming a conductive line over a substrate; forming an etch stop layer (ESL) over the conductive line, the ESL extending continuously along an upper surface of the conductive line and along an upper surface of a first dielectric layer adjacent to the conductive line, where a first lower surface of the ESL contacts the upper surface of the conductive line, and a second lower surface of the ESL contacts the upper surface of the first dielectric layer, the first lower surface being closer to the substrate than the second lower surface; forming a second dielectric layer over the ESL; forming an opening in the second dielectric layer, the opening exposing a first portion of the ESL; removing the first portion of the ESL to expose the conductive line; and filling the opening with an electrically conductive material to form a via.Type: ApplicationFiled: May 23, 2022Publication date: September 8, 2022Inventors: Chien-Han Chen, Chien-Chih Chiu, Ming-Chung Liang
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Publication number: 20220173042Abstract: An embodiment includes a method. The method includes: forming a first conductive line over a substrate; depositing a first dielectric layer over the first conductive line; depositing a second dielectric layer over the first dielectric layer, the second dielectric layer including a different dielectric material than the first dielectric layer; patterning a via opening in the first dielectric layer and the second dielectric layer, where the first dielectric layer is patterned using first etching process parameters, and the second dielectric layer is patterned using the first etching process parameters; patterning a trench opening in the second dielectric layer; depositing a diffusion barrier layer over a bottom and along sidewalls of the via opening, and over a bottom and along sidewalls of the trench opening; and filling the via opening and the trench opening with a conductive material.Type: ApplicationFiled: February 14, 2022Publication date: June 2, 2022Inventors: Chun-Te Ho, Ming-Chung Liang, Chien-Chih Chiu, Chien-Han Chen
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Patent number: 11342224Abstract: A method of forming a semiconductor device includes forming a conductive line over a substrate; forming an etch stop layer (ESL) over the conductive line, the ESL extending continuously along an upper surface of the conductive line and along an upper surface of a first dielectric layer adjacent to the conductive line, where a first lower surface of the ESL contacts the upper surface of the conductive line, and a second lower surface of the ESL contacts the upper surface of the first dielectric layer, the first lower surface being closer to the substrate than the second lower surface; forming a second dielectric layer over the ESL; forming an opening in the second dielectric layer, the opening exposing a first portion of the ESL; removing the first portion of the ESL to expose the conductive line; and filling the opening with an electrically conductive material to form a via.Type: GrantFiled: February 13, 2019Date of Patent: May 24, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien-Han Chen, Chien-Chih Chiu, Ming-Chung Liang
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Patent number: 11251127Abstract: An embodiment includes a method. The method includes: forming a first conductive line over a substrate; depositing a first dielectric layer over the first conductive line; depositing a second dielectric layer over the first dielectric layer, the second dielectric layer including a different dielectric material than the first dielectric layer; patterning a via opening in the first dielectric layer and the second dielectric layer, where the first dielectric layer is patterned using first etching process parameters, and the second dielectric layer is patterned using the first etching process parameters; patterning a trench opening in the second dielectric layer; depositing a diffusion barrier layer over a bottom and along sidewalls of the via opening, and over a bottom and along sidewalls of the trench opening; and filling the via opening and the trench opening with a conductive material.Type: GrantFiled: December 20, 2019Date of Patent: February 15, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Te Ho, Ming-Chung Liang, Chien-Chih Chiu, Chien-Han Chen
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Publication number: 20210335661Abstract: A semiconductor interconnect structure includes a conductive line electrically coupled to an active semiconductor device, a first etch stop layer formed over the conductive line, a first dielectric layer formed over the first etch stop layer, a second etch stop layer formed over the first dielectric layer, a second dielectric layer formed over the second etch stop layer, and an interconnect structure electrically coupled to the via and extending through the first etch stop layer, the first dielectric layer, the second etch stop layer, and the second dielectric layer. The interconnect structure includes a via extending through the first etch stop layer, the second etch stop layer, and the first dielectric layer and a trench extending through the second dielectric layer.Type: ApplicationFiled: February 3, 2021Publication date: October 28, 2021Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chien-Han Chen, Chien-Chih Chiu, Shih-Yu Chang, Da-Wei Lin, Y.T. Chen
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Publication number: 20200135562Abstract: A method of forming a semiconductor device includes forming a conductive line over a substrate; forming an etch stop layer (ESL) over the conductive line, the ESL extending continuously along an upper surface of the conductive line and along an upper surface of a first dielectric layer adjacent to the conductive line, where a first lower surface of the ESL contacts the upper surface of the conductive line, and a second lower surface of the ESL contacts the upper surface of the first dielectric layer, the first lower surface being closer to the substrate than the second lower surface; forming a second dielectric layer over the ESL; forming an opening in the second dielectric layer, the opening exposing a first portion of the ESL; removing the first portion of the ESL to expose the conductive line; and filling the opening with an electrically conductive material to form a via.Type: ApplicationFiled: February 13, 2019Publication date: April 30, 2020Inventors: Chien-Han Chen, Chien-Chih Chiu, Ming-Chung Liang