Abstract: A controller of a power conversion circuit, coupled to a smart power stage (SPS), controls SPS to convert an input voltage into an output voltage and provides an output current. The SPS provides a current monitoring signal to the controller. The controller includes a control loop, a sampling circuit and a current reconstruction circuit. The control loop is coupled to SPS and generates a pulse-width modulation (PWM) signal to control the operation of SPS. The sampling circuit is coupled to SPS and receives the current monitoring signal. The current monitoring signal is sampled according to PWM signal to obtain a calibration reference value. The current reconstruction circuit is coupled to the control loop and sampling circuit and generates a reconstructed current corresponding to actual output current. The reconstructed current is produced according to an input voltage, a reference voltage and PWM signal and calibrated using the calibration reference value.

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a first substrate, a capacitor within the first substrate, a diode structure within the first substrate adjacent the capacitor, and a first interconnect structure over the capacitor and the diode structure. A first conductive via of the first interconnect structure electrically couples the capacitor to the diode structure.

Abstract: The present disclosure relates to methods for assaying and controlling micro-objects in a microfluidic device. In situ-generated hydrogel barriers are provided for dividing a microfluidic chamber into areas where assaying a cell may be performed without interference from the presence of the cell itself.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The gate stack includes a gate dielectric layer and a work function layer. The gate dielectric layer is between the semiconductor substrate and the work function layer. The semiconductor device structure also includes a halogen source layer. The gate dielectric layer is between the semiconductor substrate and the halogen source layer.

Abstract: A semiconductor device structure and a formation method are provided. The method includes forming a protruding structure over a substrate. The protruding structure has multiple sacrificial layers and multiple semiconductor layers, and the sacrificial layers and the semiconductor layers have an alternating configuration. The method also includes forming a gate stack to wrap a portion of the protruding structure. The method further includes forming an epitaxial structure abutting edges of the semiconductor layers. The formation of the epitaxial structure includes forming a lower semiconductor portion on a bottom of the recess and forming an upper semiconductor portion over the lower semiconductor portion. The upper semiconductor portion and the lower semiconductor portion are oppositely doped.

Abstract: A multi-shield plate includes a plurality of windows and a plurality of vapor shields mounted to the plurality of windows, wherein each window of the plurality of windows is formed in the plate and extends through an entirety of the plate in a thickness direction. The multi-shield plate further includes a plurality of apertures in the plate, wherein each of the plurality of apertures extends through the entirety of the plate in the thickness direction and, an aperture of the plurality of apertures is aligned with a corresponding window of the plurality of windows along radius of the multi-shield plate.

Abstract: In some embodiments, the present disclosure relates to a 3D integrated circuit (IC) stack that includes a first IC die bonded to a second IC die. The first IC die includes a first semiconductor substrate, a first interconnect structure arranged on a frontside of the first semiconductor substrate, and a first bonding structure arranged over the first interconnect structure. The second IC die includes a second semiconductor substrate, a second interconnect structure arranged on a frontside of the second semiconductor substrate, and a second bonding structure arranged on a backside of the second semiconductor substrate. The first bonding structure faces the second bonding structure. Further, the 3D IC stack includes a first backside contact that extends from the second bonding structure to the backside of the second semiconductor substrate and is thermally coupled to at least one of the first or second interconnect structures.

Abstract: A circuit that includes: a photodiode configured to absorb photons and to generate photo-carriers from the absorbed photons; a first MOSFET transistor that includes: a first channel terminal coupled to a first terminal of the photodiode and configured to collect a portion of the photo-carriers generated by the photodiode; a second channel terminal; and a gate terminal coupled to a first control voltage source; a first readout circuit configured to output a first readout voltage; a second readout circuit configured to output a second readout voltage; and a current-steering circuit configured to steer the photo-carriers generated by the photodiode to one or both of the first readout circuit and the second readout circuit.

Abstract: A buffer for holding a pipe adapted to transport a fluid includes a base. The buffer further includes a plurality of fingers extending outwardly from a first side of the base, wherein a first finger of the plurality of fingers and a second finger of the plurality of fingers define a cavity for receiving the pipe, the first finger extends outwardly from a first end of the base, and the second finger extends outwardly from a central portion of the base, and a third finger of plurality of fingers extends outwardly from a second end of the base opposite the first end, wherein the second finger is between the first finger and the third finger. The buffer further includes at least one roller on a second side of the base opposite the first side.

Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a shield structure blocks the migration of charge to a semiconductor device from proximate a through substrate via (TSV). In some embodiments, the IC comprises a substrate, an interconnect structure, the semiconductor device, the TSV, and the shield structure. The interconnect structure is on a frontside of the substrate and comprises a wire. The semiconductor device is on the frontside of the substrate, between the substrate and the interconnect structure. The TSV extends completely through the substrate, from a backside of the substrate to the wire, and comprises metal. The shield structure comprises a PN junction extending completely through the substrate and directly between the semiconductor device and the TSV.

Abstract: A method includes forming bottom conductive lines over a wafer. A first magnetic tunnel junction (MTJ) stack is formed over the bottom conductive lines. Middle conductive lines are formed over the first MTJ stack. A second MTJ stack is formed over the middle conductive lines. Top conductive lines are formed over the second MTJ stack.

Abstract: An apparatus, a processing circuitry and a method for measuring a distance to an object are provided. The apparatus comprising a light source, a direct time of flight (DTOF) sensor array configured to receive a reflected signal from the object, a processing circuitry coupled to the DTOF sensor array and comprising a first time to digital converter (TDC) and a second TDC, respectively disposed on opposite sides of the DTOF sensor array, the processing circuitry configured to receive, by the first TDC, a first photon detection signal transmitted by a first pixel, receive, by the second TDC, a second photon detection signal transmitted by the first pixel, and calculate a first distance from the first pixel to the object according to a first arrival time of the first photon detection signal detected by the first TDC and a second arrival time of the second signal detected by the second TDC.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a first via disposed within a dielectric structure on a substrate, and a second via disposed within the dielectric structure and laterally separated from the first via by the dielectric structure. The first via has a first width that is smaller than a second width of the second via. An interconnect wire vertically contacts the second via and extends laterally past an outermost sidewall of the second via. A through-substrate via (TSV) is arranged over the second via and extends through the substrate. The TSV has a minimum width that is smaller than the second width of the second via. The second via has opposing outermost sidewalls that are laterally outside of the TSV.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. A semiconductor structure includes top, bottom, and middle tiers. The bottom tier includes a first interconnect structure overlying a first semiconductor substrate, and a first front-side bonding structure overlying the first interconnect structure. The middle tier interposed between and electrically coupled to the top and bottom tiers includes a second interconnect structure overlying a second semiconductor substrate, a second front-side bonding structure interposed between the top tier and the second interconnect structure, and a back-side bonding structure interposed between the second semiconductor substrate and the first front-side bonding structure.

Abstract: A method includes forming a memory stack over a substrate. A dielectric layer is deposited to cover the memory stack. An opening is formed in the dielectric layer. The opening does not expose the memory stack. A spin-orbit-torque (SOT) layer is formed in the opening. A free layer is formed over the dielectric layer to interconnect the memory stack and the SOT layer.

Abstract: A method for forming a high electron mobility transistor (HEMT) includes forming a buffer layer on a transparent substrate. The method further includes forming a barrier layer on the buffer layer. A channel region is formed in the buffer layer adjacent to the interface between the buffer layer and the barrier layer. The method further includes forming a dielectric layer on the barrier layer. The method further includes forming source/drain electrodes through the dielectric layer and the barrier layer and disposed on the buffer layer. The method further includes forming a shielding layer conformally covering the dielectric layer and the source/drain electrodes. The method further includes performing a thermal process on the source/drain electrodes.

Abstract: Image sensors and processes of forming the same are provided. An image sensor according to the present disclosure includes a first photodiode disposed between a second photodiode and a third photodiode along a direction, a first deep trench isolation (DTI) feature disposed between the first photodiode and the second photodiode, and a second DTI feature disposed between the first photodiode and the third photodiode. A depth of the first DTI feature is greater than a depth of the second DTI feature. A quantum efficiency of the second photodiode is smaller than a quantum efficiency of the first photodiode.

Abstract: The present invention provides a method for generating a virtual navigation route, by obtaining multiple navigation points each with a flag data; identifying at least two lanes from a front video data; creating a navigation characteristic image according to the flag data, the navigation points, the front video data, and the at least two lanes, wherein the navigation characteristic image has multiple dotted grids; calculating a probability of a navigation route passing through each dotted grid, and setting the dotted grid with the highest probability calculated in each row of the navigation characteristic image as a first default value; and fitting curves for the grids with the first default value as the navigation route; the navigation route is generated in real time and projected over the front video data using an augmented reality (AR) method, achieving AR effects and navigating with better representation of the traffic.

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a first substrate, a capacitor within the first substrate, a diode structure within the first substrate adjacent the capacitor, and a first interconnect structure over the capacitor and the diode structure. A first conductive via of the first interconnect structure electrically couples the capacitor to the diode structure.

Abstract: The present disclosure provides methods of fabricating a semiconductor device. A method according to one embodiment includes forming, on a substrate, a first fin formed of a first semiconductor material and a second fin formed of a second semiconductor material different from the first semiconductor material, forming a semiconductor cap layer over the first fin and the second fin, and annealing the semiconductor cap layer at a first temperature while at least a portion of the semiconductor cap layer is exposed.