Patents by Inventor Chih-An Su

Chih-An Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200279917
    Abstract: A manufacturing method of a semiconductor device includes the following steps. A semiconductor substrate with gate structures formed thereon is provided. A source/drain region is formed in the semiconductor substrate and formed between the gate structures. A dielectric layer is formed on the source/drain region and located between the gate structures. An opening penetrating the dielectric layer on the source/drain region is formed. A lower portion of a first conductive structure is formed in the opening. A dielectric spacer is formed on the lower portion and on an inner wall of the opening. An upper portion of the first conductive structure is formed in the opening and on the lower portion. The dielectric spacer surrounds the upper portion of the first conductive structure. The first conductive structure is formed by two steps for forming the dielectric spacer surrounding the upper portion and improving the electrical performance of the semiconductor device.
    Type: Application
    Filed: May 19, 2020
    Publication date: September 3, 2020
    Inventors: Te-Chang Hsu, Che-Hsien Lin, Cheng-Yeh Huang, Chun-Jen Huang, Yu-Chih Su, Yao-Jhan Wang
  • Publication number: 20200273982
    Abstract: A method includes forming a first semiconductor layer over a substrate, forming a second semiconductor layer over the first semiconductor layer, forming a first trench and a second trench through in the first semiconductor layer and the second semiconductor layer, wherein a width of the second trench is different from a width of the first trench, forming a dielectric region in the first trench and forming a first gate region in the first trench and over the dielectric region, and a second gate region in the second trench.
    Type: Application
    Filed: May 12, 2020
    Publication date: August 27, 2020
    Inventors: Chun-Wai Ng, Hsueh-Liang Chou, Po-Chih Su, Ruey-Hsin Liu
  • Publication number: 20200275149
    Abstract: A multi-screen synchronized playback system including a group, a network time protocol (NTP) server is provided. The group includes a plurality of playback devices connected to a local area network (LAN). One of the playback devices is designated as a master playback device, the remaining playback devices of the playback devices are designated as slave playback devices. The NTP server is connected to the LAN and provides a standard time information for each of the playback devices. In preparing state, the master playback device sends a first type packet to each of the slave playback devices through the local area network, and the first type packet includes a starting playback time information according to the standard time information provided by the NTP server. A multi-screen synchronized playback method is also provided.
    Type: Application
    Filed: February 27, 2019
    Publication date: August 27, 2020
    Applicant: Novatek Microelectronics Corp.
    Inventors: Yung-Chih Su, Hong-Ruei Jhang
  • Patent number: 10700163
    Abstract: A manufacturing method of a semiconductor device includes the following steps. A semiconductor substrate with gate structures formed thereon is provided. A source/drain region is formed in the semiconductor substrate and formed between the gate structures. A dielectric layer is formed on the source/drain region and located between the gate structures. An opening penetrating the dielectric layer on the source/drain region is formed. A lower portion of a first conductive structure is formed in the opening. A dielectric spacer is formed on the lower portion and on an inner wall of the opening. An upper portion of the first conductive structure is formed in the opening and on the lower portion. The dielectric spacer surrounds the upper portion of the first conductive structure. The first conductive structure is formed by two steps for forming the dielectric spacer surrounding the upper portion and improving the electrical performance of the semiconductor device.
    Type: Grant
    Filed: November 18, 2018
    Date of Patent: June 30, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Te-Chang Hsu, Che-Hsien Lin, Cheng-Yeh Huang, Chun-Jen Huang, Yu-Chih Su, Yao-Jhan Wang
  • Publication number: 20200192579
    Abstract: A method for oversubscribing a host memory of a host running a virtual machine monitor (VMM), comprising, examining a virtual machine (VM) memory for a VM for metadata associated with the VM memory, the metadata maintained by a guest OS running on the VM, collecting the metadata for the VM memory, and managing the VM memory using the metadata for oversubscribing a host memory.
    Type: Application
    Filed: December 12, 2019
    Publication date: June 18, 2020
    Inventors: Horacio Andres Lagar Cavilla, Adin Matthew Scannell, Timothy James Smith, Peter Feiner, Mushfiq Mahmood, David Richard Scannell, Jing Chih Su
  • Patent number: 10686065
    Abstract: A method includes forming a first semiconductor layer over a substrate, forming a second semiconductor layer over the first semiconductor layer, forming a first trench and a second trench through in the first semiconductor layer and the second semiconductor layer, wherein a width of the second trench is different from a width of the first trench, forming a dielectric region in the first trench and forming a first gate region in the first trench and over the dielectric region, and a second gate region in the second trench.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: June 16, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wai Ng, Hsueh-Liang Chou, Po-Chih Su, Ruey-Hsin Liu
  • Patent number: 10680100
    Abstract: The present disclosure relates to a high voltage transistor device having a field structure that includes at least one conduction unit, and a method of formation. In some embodiments, the high voltage transistor device has a gate electrode disposed over a substrate between a source region and a drain region located within the substrate. A dielectric layer laterally extends from over the gate electrode to over a drift region between the gate electrode and the drain region. A field structure is located within the first ILD layer. The field structure includes a conduction unit having a vertically elongated shape and vertically extending from a top surface of the dielectric layer and a top surface of the first ILD layer.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: June 9, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Chih Su, Hsueh-Liang Chou, Ruey-Hsin Liu
  • Publication number: 20200169708
    Abstract: A projection apparatus and its operation method are provided. The projection apparatus includes a light-emitting device, a driving circuit coupled to the light-emitting device, and a control circuit receiving at least one video frame and analyzing color content of the at least one video frame. According to at least one control signal, the driving circuit drives the light-emitting device to generate a projected beam. The control circuit selects a highlight mode or a normal mode as a selected mode according to the color content and correspondingly sets at least one control signal to the driving circuit according to the selected mode. A brightness of the projected beam of the light-emitting device in the highlight mode is greater than that in the normal mode.
    Type: Application
    Filed: November 20, 2019
    Publication date: May 28, 2020
    Applicant: Coretronic Corporation
    Inventors: Wei-Chih Su, Sheng-Yu Chiu, Po-Yen Wu, Jung-Chi Chen, Chih-Lin Wang
  • Patent number: 10636904
    Abstract: The present disclosure, in some embodiments, relates to a transistor device having a field plate. The transistor device has a gate electrode disposed over a substrate between a source region and a drain region. One or more dielectric layers are arranged over the gate electrode, and a field plate is arranged over the one or more dielectric layers. The field plate extends from a first outermost sidewall that is directly over an upper surface of the gate electrode to a second outermost sidewall that is between the gate electrode and the drain region and that extends to below the upper surface of the gate electrode.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: April 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsueh-Liang Chou, Dah-Chuen Ho, Hui-Ting Lu, Po-Chih Su, Pei-Lun Wang, Yu-Chang Jong
  • Publication number: 20200127089
    Abstract: A manufacturing method of a semiconductor device includes the following steps. A semiconductor substrate with gate structures formed thereon is provided. A source/drain region is formed in the semiconductor substrate and formed between the gate structures. A dielectric layer is formed on the source/drain region and located between the gate structures. An opening penetrating the dielectric layer on the source/drain region is formed. A lower portion of a first conductive structure is formed in the opening. A dielectric spacer is formed on the lower portion and on an inner wall of the opening. An upper portion of the first conductive structure is formed in the opening and on the lower portion. The dielectric spacer surrounds the upper portion of the first conductive structure. The first conductive structure is formed by two steps for forming the dielectric spacer surrounding the upper portion and improving the electrical performance of the semiconductor device.
    Type: Application
    Filed: November 18, 2018
    Publication date: April 23, 2020
    Inventors: Te-Chang Hsu, Che-Hsien Lin, Cheng-Yeh Huang, Chun-Jen Huang, Yu-Chih Su, Yao-Jhan Wang
  • Patent number: 10540092
    Abstract: A method for oversubscribing a host memory of a host running a virtual machine monitor (VMM), comprising, examining a virtual machine (VM) memory for a VM for metadata associated with the VM memory, the metadata maintained by a guest OS running on the VM, collecting the metadata for the VM memory, and managing the VM memory using the metadata for oversubscribing a host memory.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: January 21, 2020
    Assignee: Google LLC
    Inventors: Horacio Andres Lagar Cavilla, Adin Matthew Scannell, Timothy James Smith, Peter Feiner, Mushfiq Mahmood, David Richard Scannell, Jing Chih Su
  • Publication number: 20200020802
    Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a source region and a drain region within a substrate. A gate structure is formed over the substrate and between the source region and the drain region. One or more dielectric layers are formed over the gate structure, and a first inter-level dielectric (ILD) layer is formed over the one or more dielectric layers. The first ILD layer laterally surrounds the gate structure. The first ILD layer is etched to define contact openings and a field plate opening. The contact openings and the field plate opening are filled with a conductive material.
    Type: Application
    Filed: September 21, 2019
    Publication date: January 16, 2020
    Inventors: Hsueh-Liang Chou, Dah-Chuen Ho, Hui-Ting Lu, Po-Chih Su, Pei-Lun Wang, Yu-Chang Jong
  • Publication number: 20200013888
    Abstract: The present disclosure relates to a high voltage transistor device having a field structure that includes at least one conduction unit, and a method of formation. In some embodiments, the high voltage transistor device has a gate electrode disposed over a substrate between a source region and a drain region located within the substrate. A dielectric layer laterally extends from over the gate electrode to over a drift region between the gate electrode and the drain region. A field structure is located within the first ILD layer. The field structure includes a conduction unit having a vertically elongated shape and vertically extending from a top surface of the dielectric layer and a top surface of the first ILD layer.
    Type: Application
    Filed: July 3, 2018
    Publication date: January 9, 2020
    Inventors: Po-Chih Su, Hsueh-Liang Chou, Ruey-Hsin Liu
  • Publication number: 20200006489
    Abstract: A transistor includes a first gate electrode and a second gate electrode over a substrate and on opposite sides of a drain region, a first source region and the drain region on opposite sides of the first gate electrode, a second source region and the drain region on opposite sides of the second gate electrode, a first doped well formed under the first source region, a second doped well formed under the first source region, wherein the first doped well is embedded in the second doped well, and wherein a doping density of the first doped well is greater than a doping density of the second doped well and a body contact region adjacent to the first source region, wherein sidewalls of the body contact region are aligned with sidewalls of the first source region from a top view.
    Type: Application
    Filed: September 12, 2019
    Publication date: January 2, 2020
    Inventors: Hsueh-Liang Chou, Chun-Wai Ng, Po-Chih Su, Ruey-Hsin Liu
  • Patent number: 10510880
    Abstract: A device includes a semiconductor region of a first conductivity type, a trench extending into the semiconductor region, and a conductive field plate in the trench. A first dielectric layer separates a bottom and sidewalls of the field plate from the semiconductor region. A main gate is disposed in the trench and overlapping the field plate. A second dielectric layer is disposed between and separating the main gate and the field plate from each other. A Doped Drain (DD) region of the first conductivity type is under the second dielectric layer, wherein an edge portion of the main gate overlaps the DD region. A body region includes a first portion at a same level as a portion of the main gate, and a second portion at a same level as, and contacting, the DD region, wherein the body region is of a second conductivity type opposite the first conductivity type.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wai Ng, Hsueh-Liang Chou, Ruey-Hsin Liu, Po-Chih Su
  • Patent number: 10446682
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a first and a second fin structures, a first, a second and a third isolation structures, and a first and a second gate structures. The first and second fin structures are disposed in a substrate. The first isolation structure is disposed in the substrate and surrounds the first and second fin structures. The second isolation structure is disposed in the first fin structure, and a top surface of the second isolation structure is leveled with a top surface of the first and second fin structures. The third isolation structure is disposed in the second fin shaped structure, and a top surface of the third isolation structure is lower than the top surface of the first and second fin structures. The first and second gate structures are disposed on the second and third isolation structures, respectively.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: October 15, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chi-Hsuan Cheng, Cheng-Pu Chiu, Yu-Chih Su, Chih-Yi Wang, Chin-Yang Hsieh, Tien-Shan Hsu, Yao-Jhan Wang
  • Publication number: 20190267377
    Abstract: A device includes a vertical transistor comprising a first gate in a first trench, wherein the first gate comprises a dielectric layer and a gate region over the dielectric layer, and a second gate in a second trench, a high voltage lateral transistor immediately adjacent to the vertical transistor and a low voltage lateral transistor, wherein the high voltage lateral transistor is between the vertical transistor and the low voltage lateral transistor.
    Type: Application
    Filed: May 7, 2019
    Publication date: August 29, 2019
    Inventors: Chun-Wai Ng, Hsueh-Liang Chou, Po-Chih Su, Ruey-Hsin Liu
  • Publication number: 20190174653
    Abstract: A liquid-cooling heat dissipating module includes a liquid-cooling radiator, a liquid-cooling head, a liquid pump, a first pipe, a second pipe and a shielding cover. The liquid-cooling radiator, the liquid-cooling head and the liquid pump are in fluid communication with each other through the first pipe, the second pipe and an external pump tube of the liquid pump. The liquid-cooling head is in thermal contact with a heat source. The liquid pump drives a fluid medium to circularly flow within the closed loop. At least a part of the liquid pump is sheltered by the shielding cover. Consequently, at least a portion of a sound generated by the liquid pump is obstructed from outputting to surroundings.
    Type: Application
    Filed: January 10, 2018
    Publication date: June 6, 2019
    Inventors: MU-SHU FAN, CHE-CHIA CHANG, CHIEN-CHIH SU
  • Patent number: 10304829
    Abstract: A device includes a vertical transistor and a lateral transistor on a substrate, wherein the vertical transistor comprises a first gate in a first trench, a second gate in a second trench, a source and a drain, wherein the source and the drain are on opposite sides of the first trench and the lateral transistor and the drain are on opposite sides of the second trench.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: May 28, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wai Ng, Hsueh-Liang Chou, Po-Chih Su, Ruey-Hsin Liu
  • Publication number: 20190148550
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a first and a second fin structures, a first, a second and a third isolation structures, and a first and a second gate structures. The first and second fin structures are disposed in a substrate. The first isolation structure is disposed in the substrate and surrounds the first and second fin structures. The second isolation structure is disposed in the first fin structure, and a top surface of the second isolation structure is leveled with a top surface of the first and second fin structures. The third isolation structure is disposed in the second fin shaped structure, and a top surface of the third isolation structure is lower than the top surface of the first and second fin structures. The first and second gate structures are disposed on the second and third isolation structures, respectively.
    Type: Application
    Filed: January 9, 2019
    Publication date: May 16, 2019
    Inventors: Chi-Hsuan Cheng, Cheng-Pu Chiu, Yu-Chih Su, Chih-Yi Wang, Chin-Yang Hsieh, Tien-Shan Hsu, Yao-Jhan Wang