Patents by Inventor Chih-Chang Lin

Chih-Chang Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Amplifier inductor sharing for inductive peaking and method therefor
    Patent number: 9276537
    Abstract: A method of sharing inductors for inductive peaking of an amplifier includes calculating a single stage inductance of a single stage for inductive peaking in order to have a stable impulse response. The method further includes determining a number of stages for shared inductance for inductive peaking. The method further includes sharing at least two inductors having the shared inductance among the determined number of stages for inductive peaking.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: March 1, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tao Wen Chung, Chan-Hong Chern, Ming-Chieh Huang, Chih-Chang Lin, Yuwen Swei
  • Voltage regulator
    Patent number: 9275719
    Abstract: A voltage regulator includes an amplifier, an output stage coupled with the amplifier, at least one back-bias circuit, and an output end coupled with the output stage and with the amplifier. The output stage includes at least one transistor having a bulk and a drain. The at least one back-bias circuit is coupled with the bulk of the at least one transistor. The output end is configured to be coupled with a memory array and with an output end of another voltage regulator. The back-bias circuit is configured to reduce a contention current between the voltage regulator and the other voltage regulator during a standby mode.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: March 1, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Chieh Huang, Chan-Hong Chern, Tien Chun Yang, Chih-Chang Lin, Yuwen Swei
  • Level shifting apparatus and method of using the same
    Patent number: 9270276
    Abstract: A level shifting apparatus includes a first capacitor, a first side of the first capacitor configured to receive a first voltage. The level shifting apparatus further includes an edge detector configured to receive the first voltage. The level shifting apparatus further includes an output inverter connected to a second side of the first capacitor, the output inverter configured to output an voltage-level shifted signal of the level shifting apparatus. The level shifting apparatus further includes a latch loop configured to receive feedback the output signal to an input of the output inverter, wherein the edge detector is configured to selectively interrupt feedback of the output signal to the input of the output inverter.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: February 23, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Ching (Jim) Huang, Chan-Hong Chern, Ming-Chieh Huang, Chih-Chang Lin
  • LEVEL SHIFTING APPARATUS AND METHOD OF USING THE SAME
    Publication number: 20160036442
    Abstract: A level shifting apparatus includes a first capacitor, a first side of the first capacitor configured to receive a first voltage. The level shifting apparatus further includes an edge detector configured to receive the first voltage. The level shifting apparatus further includes an output inverter connected to a second side of the first capacitor, the output inverter configured to output an voltage-level shifted signal of the level shifting apparatus. The level shifting apparatus further includes a latch loop configured to receive feedback the output signal to an input of the output inverter, wherein the edge detector is configured to selectively interrupt feedback of the output signal to the input of the output inverter.
    Type: Application
    Filed: July 30, 2014
    Publication date: February 4, 2016
    Inventors: Tsung-Ching (Jim) HUANG, Chan-Hong CHERN, Ming-Chieh HUANG, Chih-Chang LIN
  • Current generator and method of operating
    Patent number: 9236799
    Abstract: A current generator includes an amplifier having a first terminal configured to receive an input voltage, at least one tunable resistor coupled to a second terminal of the amplifier, a resistor calibration circuit coupled to the at least one tunable resistor, and at least one transistor. A gate of the at least one transistor is coupled to an output of the amplifier, and a terminal of the at least one transistor is coupled to the at least one tunable resistor or a load. The resistor calibration circuit is configured to adjust a resistance setting of the at least one tunable resistor to control a current level of the current generator based on a power supply voltage or a current of a reference resistor.
    Type: Grant
    Filed: October 29, 2013
    Date of Patent: January 12, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Chieh Huang, Chan-Hong Chern, Chih-Chang Lin
  • Input/output circuit
    Patent number: 9214933
    Abstract: A circuit includes a first power node configured to carry a voltage K·VDD, a second power node configured to carry a zero reference level, an output node, K P-type transistors serially coupled between the first power node and the output node, and K N-type transistors serially coupled between the second power node and the output node. Gates of the K P-type transistors are configured to receive biasing signals set at one or more voltage levels in a manner that one or more absolute values of source-gate voltages or absolute values of drain-gate voltages are equal to or less than VDD. Gates of the K N-type transistors are configured to receive biasing signals set at one or more voltage levels in a manner that one or more absolute values of gate-source voltages or gate-drain voltages are equal to or less than VDD.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: December 15, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chan-Hong Chern, Tsung-Ching Huang, Chih-Chang Lin, Ming-Chieh Huang, Fu-Lung Hsueh
  • Input/output circuit having an inductor
    Patent number: 9214805
    Abstract: An input/output (I/O) circuit includes an electrostatic discharge (ESD) protection circuit electrically coupled with an output node of the I/O circuit. At least one inductor and at least one loading are electrically coupled in a series fashion and between the output node of the I/O circuit and a power line. A circuitry is electrically coupled with a node between the at least one inductor and the at least one loading. The circuitry is operable to increase a current flowing through the at least one inductor during a signal transition. The circuitry comprises at least one pre-driver stage having at least one output node, and the at least one output node of the at least one pre-driver stage is electrically coupled with at least one input node of a driver stage.
    Type: Grant
    Filed: December 9, 2013
    Date of Patent: December 15, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tao Wen Chung, Chan-Hong Chern, Ming-Chieh Huang, Chih-Chang Lin, Yuwen Swei
  • PIXEL CIRCUIT AND METHOD OF ADJUSTING BRIGHTNESS OF PIXEL CIRCUIT
    Publication number: 20150356917
    Abstract: A current value of a first pixel and/or a current value of a second pixel of a display are adjusted until a value of a current difference is within a predetermined range. The current value of the first pixel corresponds to a brightness level of the first pixel. The current value of the second pixel corresponds to a brightness level of the second pixel. Adjusting the current value of the first pixel involves adjusting a threshold voltage value of a transistor of the first pixel. Adjusting the current value of the second pixel involves adjusting a threshold voltage value of a transistor of the second pixel.
    Type: Application
    Filed: August 14, 2015
    Publication date: December 10, 2015
    Inventors: Tsung-Ching HUANG, Chan-Hong CHERN, Tao Wen CHUNG, Ming-Chieh HUANG, Chih-Chang LIN
  • Charge pump initialization device, integrated circuit having charge pump initialization device, and method of operation
    Patent number: 9209681
    Abstract: In an initialization phase of a charge pump, an input signal is supplied to an input electrode of a capacitor of the charge pump and to an initialization device of the charge pump. An initialization signal is supplied to the initialization device of the charge pump. The initialization device supplies an output signal to an output electrode of the capacitor. The output signal has a high level and a low level corresponding to a high level and a low level of the input signal, the input signal and the output signal causing a charge to be accumulated in the capacitor. In a pumping operation phase following the initialization phase, the initialization signal is removed from the initialization device to place the output electrode of the capacitor in a floating state, and a pumping action is performed with the charge accumulated in the capacitor.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: December 8, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chan-Hong Chern, Chih-Chang Lin, Tsung-Ching Huang, Ming-Chieh Huang
  • Dummy metal gate structures to reduce dishing during chemical-mechanical polishing
    Patent number: 9209182
    Abstract: The described embodiments of mechanisms for placing dummy gate structures next to and/or near a number of wide gate structures reduce dishing effect for gate structures during chemical-mechanical polishing of gate layers. The arrangements of dummy gate structures and the ranges of metal pattern density have been described. Wide gate structures, such as analog devices, can greatly benefit from the reduction of dishing effect.
    Type: Grant
    Filed: July 8, 2013
    Date of Patent: December 8, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chan-Hong Chern, Chih-Chang Lin, Jacklyn Chang, Julie Tran
  • Delay line circuit with variable delay line unit
    Patent number: 9203387
    Abstract: A delay line circuit comprises a plurality of delay units configured to receive an input signal and modify the input signal to produce a first output signal. The delay line circuit also comprises a variable delay line unit that comprises an input end configured to receive the first output signal; an output end configured to output a second output signal; a first line between the input end and the output end, the first line comprising, in series, a first inverter, a second inverter, a first speed control unit, and a third inverter; a second line between the input end and the output end, the second line comprising, in series, a fourth inverter, a second speed control unit, a fifth inverter, and a sixth inverter. The delay line circuit is also configured to selectively transmit the received first output signal through one of the first line or the second line.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: December 1, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Chieh Huang, Chan-Hong Chern, Tsung-Ching Huang, Chih-Chang Lin, Fu-Lung Hsueh
  • Drivers having T-coil structures
    Patent number: 9197195
    Abstract: A driver includes a first driver stage having a first T-coil structure. The first T-coil structure includes a first set of inductors each being operable to provide a first inductance. The first T-coil structure further includes a second set of inductors electrically coupled with the first set of inductors, wherein the second set of inductors each are operable to provide a second inductance.
    Type: Grant
    Filed: October 22, 2014
    Date of Patent: November 24, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Chieh Huang, Tao Wen Chung, Chan-Hong Chern, Chih-Chang Lin, Yuwen Swei, Chiang Pu
  • APPARATUS HAVING PROGRAMMABLE TAPS AND METHOD OF USING THE SAME
    Publication number: 20150319017
    Abstract: An apparatus includes a plurality of delay elements configured to delay a respective input signal and to output a respective delayed signal. The apparatus also includes a weight generator configured to generate a plurality of tap weights based on the delayed signals. The apparatus further includes a tap controller configured to generate tap weight enabling signals corresponding to one or more of the tap weights if the corresponding tap weights are greater than a predetermined threshold value. The tap controller is also configured to generate a set of bias factors based on corresponding tap weights of the plurality of tap weights.
    Type: Application
    Filed: July 9, 2015
    Publication date: November 5, 2015
    Inventors: Ming-Chieh HUANG, Jing Jing CHEN, Chan-Hong CHERN, Tao Wen CHUNG, Chih-Chang LIN, Yuwen SWEI
  • VOLTAGE SUPPLY UNIT AND METHOD FOR OPERATING THE SAME
    Publication number: 20150263618
    Abstract: A voltage supply unit including a regulator unit, a voltage divider and a first current mirror. The regulator unit is configured to receive a first voltage signal and a second voltage signal, and is configured to generate a third voltage signal. The voltage divider is connected between the first current mirror and the regulator unit, and controls the second voltage signal. The first current mirror is connected to the regulator unit, an input voltage supply and the voltage divider. The first current mirror is configured to generate a first current signal and a second current signal, the second current signal is mirrored from the first current signal, the first current signal is controlled by the third voltage signal and the second current signal controls an output voltage supply signal.
    Type: Application
    Filed: March 14, 2014
    Publication date: September 17, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chan-Hong CHERN, Tsung-Ching HUANG, Chih-Chang LIN, Ming-Chieh HUANG, Fu-Lung HSUEH
  • Method and apparatus for feedback-based resistance calibration
    Patent number: 9134360
    Abstract: A circuit has a first circuit module including a first resistor and first and second transistors coupled in parallel with the first resistor. The first resistor and the first and second transistors are coupled together at a first node. An equivalent resistance across the first circuit module increases as a voltage of the first node is increased from a first voltage to a second voltage, and the equivalent resistance across the first circuit module decreases as the voltage of the first node is increased from the second voltage to a third voltage.
    Type: Grant
    Filed: July 12, 2012
    Date of Patent: September 15, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tao Wen Chung, Chan-Hong Chern, Ming-Chieh Huang, Chih-Chang Lin, Yuwen Swei
  • VOLTAGE REGULATOR
    Publication number: 20150243341
    Abstract: A voltage regulator includes an amplifier, an output stage coupled with the amplifier, at least one back-bias circuit, and an output end coupled with the output stage and with the amplifier. The output stage includes at least one transistor having a bulk and a drain. The at least one back-bias circuit is coupled with the bulk of the at least one transistor. The output end is configured to be coupled with a memory array and with an output end of another voltage regulator. The back-bias circuit is configured to reduce a contention current between the voltage regulator and the other voltage regulator during a standby mode.
    Type: Application
    Filed: April 28, 2015
    Publication date: August 27, 2015
    Inventors: Ming-Chieh HUANG, Chan-Hong CHERN, Tien Chun YANG, Chih-Chang LIN, Yuwen SWEI
  • INPUT/OUTPUT CIRCUIT
    Publication number: 20150244360
    Abstract: A circuit includes a first power node configured to carry a voltage K·VDD, a second power node configured to carry a zero reference level, an output node, K P-type transistors serially coupled between the first power node and the output node, and K N-type transistors serially coupled between the second power node and the output node. Gates of the K P-type transistors are configured to receive biasing signals set at one or more voltage levels in a manner that one or more absolute values of source-gate voltages or absolute values of drain-gate voltages are equal to or less than VDD. Gates of the K N-type transistors are configured to receive biasing signals set at one or more voltage levels in a manner that one or more absolute values of gate-source voltages or gate-drain voltages are equal to or less than VDD.
    Type: Application
    Filed: February 25, 2014
    Publication date: August 27, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chan-Hong CHERN, Tsung-Ching HUANG, Chih-Chang LIN, Ming-Chieh HUANG, Fu-Lung HSUEH
  • CHARGE PUMP INITIALIZATION DEVICE, INTEGRATED CIRCUIT HAVING CHARGE PUMP INITIALIZATION DEVICE, AND METHOD OF OPERATION
    Publication number: 20150244258
    Abstract: In an initialization phase of a charge pump, an input signal is supplied to an input electrode of a capacitor of the charge pump and to an initialization device of the charge pump. An initialization signal is supplied to the initialization device of the charge pump. The initialization device supplies an output signal to an output electrode of the capacitor. The output signal has a high level and a low level corresponding to a high level and a low level of the input signal, the input signal and the output signal causing a charge to be accumulated in the capacitor. In a pumping operation phase following the initialization phase, the initialization signal is removed from the initialization device to place the output electrode of the capacitor in a floating state, and a pumping action is performed with the charge accumulated in the capacitor.
    Type: Application
    Filed: February 25, 2014
    Publication date: August 27, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chan-Hong CHERN, Chih-Chang LIN, Tsung-Ching HUANG, Ming-Chieh HUANG
  • DELAY LINE CIRCUIT WITH VARIABLE DELAY LINE UNIT
    Publication number: 20150244357
    Abstract: A delay line circuit comprises a plurality of delay units configured to receive an input signal and modify the input signal to produce a first output signal. The delay line circuit also comprises a variable delay line unit that comprises an input end configured to receive the first output signal; an output end configured to output a second output signal; a first line between the input end and the output end, the first line comprising, in series, a first inverter, a second inverter, a first speed control unit, and a third inverter; a second line between the input end and the output end, the second line comprising, in series, a fourth inverter, a second speed control unit, a fifth inverter, and a sixth inverter. The delay line circuit is also configured to selectively transmit the received first output signal through one of the first line or the second line.
    Type: Application
    Filed: February 24, 2014
    Publication date: August 27, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Chieh HUANG, Chan-Hong CHERN, Tsung-Ching HUANG, Chih-Chang LIN, Fu-Lung HSUEH
  • Apparatus having programmable taps
    Patent number: 9094249
    Abstract: An apparatus comprises a plurality of delay elements connected in series. Each delay element is configured to delay a respective input signal and to output a respective delayed signal. The apparatus also comprises a weight generator configured to generate a plurality of tap weights based on the delayed signals. The apparatus further comprises a tap controller configured to (1) generate tap weight enabling signals corresponding to one or more of the tap weights based on a determination that the corresponding tap weights are greater than a predetermined threshold value, and (2) generate a set of bias factors. The apparatus additionally comprises a summer configured to output a weighted signal based on the delayed signals, the tap weight enabling signals, the tap weights, and the bias factors.
    Type: Grant
    Filed: January 22, 2015
    Date of Patent: July 28, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Chieh Huang, Jing Jing Chen, Chan-Hong Chern, Tao Wen Chung, Chih-Chang Lin, Yuwen Swei