Patents by Inventor Chih-Chang Lin
Chih-Chang Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210091245Abstract: The present disclosure provides a photo sensing device, the photo sensing device includes a substrate, including a silicon layer at a front surface, a photosensitive member extending into and at least partially surrounded by the silicon layer, and a superlattice layer disposed between the photosensitive member and the silicon layer, wherein the superlattice layer includes a first material and a second material different from the first material, a first concentration of the second material at a portion of the superlattice layer proximal to the photosensitive member is greater than a second concentration of the second material at a portion of the superlattice layer distal to the photosensitive member.Type: ApplicationFiled: July 6, 2020Publication date: March 25, 2021Inventors: CHAN-HONG CHERN, WEIWEI SONG, CHIH-CHANG LIN, LAN-CHOU CHO, MIN-HSIANG HSU
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Patent number: 10921891Abstract: Systems and methods for authentication code entry in touch-sensitive screen enabled devices are disclosed. In one embodiment, a method for entering authentication value data to a data entry device that comprises at least one computer processor and a touch-sensitive screen may include: (1) the touch-sensitive screen sensing a control touch on the touch-sensitive screen; (2) the touch-sensitive screen sensing a release of the control touch from the touch-sensitive screen; (3) the at least one computer processor determining a number of first touches sensed by the touch-sensitive screen in a period between the sensing of the control touch and the sensing of the release of the control touch; and (4) the at least one computer processor using the number of first touches to represent a value in an authentication code.Type: GrantFiled: March 23, 2018Date of Patent: February 16, 2021Assignee: VeriFone, Inc.Inventors: Chih-Chang Lin, Chan He Lin
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Patent number: 10855280Abstract: A circuit receives an input signal that switches between reference and first voltage levels, a power node carries a second voltage level, and a set of transistors is coupled between the power node and an output node. The second voltage level is a multiple of the first voltage level, and the multiple and a number of the transistors have a same value greater than two. A control signal circuit includes a level shifting circuit including a series of capacitive devices paired with latch circuits, a number of the pairs being one less than the value of the multiple, and, responsive to the input signal, outputs a control signal to a gate of a transistor of the first set of transistors closest to the power node, the control signal switching between the second voltage level and a third voltage level equal to the second voltage level minus the first voltage level.Type: GrantFiled: May 14, 2020Date of Patent: December 1, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chan-Hong Chern, Tsung-Ching Huang, Chih-Chang Lin, Ming-Chieh Huang, Fu-Lung Hsueh
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Patent number: 10778203Abstract: A clock generation circuit includes: a two-phase clock generation circuit including first and second branches correspondingly configured to generate a first phase clock signal and a second phase clock signal based correspondingly on a non-inverted clock signal and an inverted clock signal, the first and second branches being cross-coupled with each other; an inverter configured to generate the inverted clock signal based on an input clock signal; and a delay circuit which is non-inverter-based and which is configured to generate the non-inverted clock signal based on the input clock signal, the delay circuit having a predetermined delay.Type: GrantFiled: November 18, 2019Date of Patent: September 15, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tien-Chun Yang, Chih-Chang Lin, Ming-Chieh Huang
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Publication number: 20200287528Abstract: A circuit includes a first power node configured to carry a first voltage having a first voltage level, a second power node configured to carry a second voltage having a second voltage level, an output node, and first and second cascode transistors coupled between the first power node and the output node and to each other at a node. A bias circuit uses the first and second cascode transistors to generate an output signal at the output node that transitions between the first voltage level and a third voltage level, and a delay circuit generates a transition in a first signal from one of the first or second voltage levels to the other of the first or second voltage levels, the transition having a time delay based on the output signal. A contending transistor couples the node to the second power node responsive to the first signal.Type: ApplicationFiled: May 26, 2020Publication date: September 10, 2020Inventors: Chan-Hong CHERN, Tsung -Ching HUANG, Chih-Chang LIN, Ming-Chieh HUANG, Fu-Lung HSUEH
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Publication number: 20200274535Abstract: A circuit receives an input signal that switches between reference and first voltage levels, a power node carries a second voltage level, and a set of transistors is coupled between the power node and an output node. The second voltage level is a multiple of the first voltage level, and the multiple and a number of the transistors have a same value greater than two. A control signal circuit includes a level shifting circuit including a series of capacitive devices paired with latch circuits, a number of the pairs being one less than the value of the multiple, and, responsive to the input signal, outputs a control signal to a gate of a transistor of the first set of transistors closest to the power node, the control signal switching between the second voltage level and a third voltage level equal to the second voltage level minus the first voltage level.Type: ApplicationFiled: May 14, 2020Publication date: August 27, 2020Inventors: Chan-Hong CHERN, Tsung-Ching HUANG, Chih-Chang LIN, Ming-Chieh HUANG, Fu-Lung HSUEH
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Patent number: 10686434Abstract: A circuit includes a first power node configured to carry a first voltage having a first voltage level, an output node, a node coupled between the first power node and the output node, and a contending transistor coupled between the node and a second power node configured to carry a second voltage having a second voltage level. The circuit generates a signal at the output node that ranges between the first voltage level and a third voltage level, the contending transistor couples the node with the second power node responsive to the signal, a difference between the first voltage level and the second voltage level has a first magnitude, a difference between the first voltage level and the third voltage level has a second magnitude, and the second magnitude is a multiple of the first magnitude having a value greater than one.Type: GrantFiled: November 30, 2018Date of Patent: June 16, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chan-Hong Chern, Tsung-Ching Huang, Chih-Chang Lin, Ming-Chieh Huang, Fu-Lung Hsueh
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Patent number: 10673437Abstract: A level-shifting circuit includes an input device configured to receive an input signal capable of switching between a reference voltage level and a first voltage level, and a set of capacitive devices paired in series with latch circuits. A first capacitive device of the set is coupled with an output of the input device, and each capacitive device and latch circuit pair is configured to upshift a corresponding received signal by an amount equal to a difference between the first voltage level and the reference voltage level.Type: GrantFiled: January 7, 2019Date of Patent: June 2, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chan-Hong Chern, Tsung-Ching Huang, Chih-Chang Lin, Ming-Chieh Huang, Fu-Lung Hsueh
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Publication number: 20200083872Abstract: A clock generation circuit includes: a two-phase clock generation circuit including first and second branches correspondingly configured to generate a first phase clock signal and a second phase clock signal based correspondingly on a non-inverted clock signal and an inverted clock signal, the first and second branches being cross-coupled with each other; an inverter configured to generate the inverted clock signal based on an input clock signal; and a delay circuit which is non-inverter-based and which is configured to generate the non-inverted clock signal based on the input clock signal, the delay circuit having a predetermined delay.Type: ApplicationFiled: November 18, 2019Publication date: March 12, 2020Inventors: Tien-Chun YANG, Chih-Chang LIN, Ming-Chieh HUANG
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Patent number: 10546528Abstract: A current value of a first pixel and/or a current value of a second pixel of a display are adjusted until a value of a current difference is within a predetermined range. The current value of the first pixel corresponds to a brightness level of the first pixel. The current value of the second pixel corresponds to a brightness level of the second pixel. Adjusting the current value of the first pixel involves adjusting a threshold voltage value of a transistor of the first pixel. Adjusting the current value of the second pixel involves adjusting a threshold voltage value of a transistor of the second pixel.Type: GrantFiled: August 14, 2015Date of Patent: January 28, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsung-Ching Huang, Chan-Hong Chern, Tao Wen Chung, Ming-Chieh Huang, Chih-Chang Lin
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Patent number: 10536146Abstract: An edge detector includes an output node selectively coupled to a first voltage node through a first transistor, the first voltage node having a first voltage level, and a second transistor configured to continuously couple the output node to a second voltage node having a second voltage level. A capacitor includes a first terminal coupled to a gate of the first transistor and a second terminal configured to receive an input signal.Type: GrantFiled: May 17, 2019Date of Patent: January 14, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsung-Ching (Jim) Huang, Chan-Hong Chern, Ming-Chieh Huang, Chih-Chang Lin
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Patent number: 10483954Abstract: A clock generation circuit includes: a two-phase clock generation circuit configured to generate a first phase clock signal and a second phase clock signal based correspondingly on a non-inverted clock signal and an inverted clock signal; an inverter configured to generate the inverted clock signal based on an input clock signal; and a delay circuit which is non-inverter-based and which is configured to generate the non-inverted clock signal based on the input clock signal, the delay circuit having a predetermined delay sufficient to induce symmetry in the first and second phase clock signals such that durational midpoints of overlapping opposite phases of the first and second phase clock signals are substantially aligned.Type: GrantFiled: April 24, 2019Date of Patent: November 19, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tien-Chun Yang, Chih-Chang Lin, Ming-Chieh Huang
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Publication number: 20190294246Abstract: Systems and methods for authentication code entry in touch-sensitive screen enabled devices are disclosed. In one embodiment, a method for entering authentication value data to a data entry device that comprises at least one computer processor and a touch-sensitive screen may include: (1) the touch-sensitive screen sensing a control touch on the touch-sensitive screen; (2) the touch-sensitive screen sensing a release of the control touch from the touch-sensitive screen; (3) the at least one computer processor determining a number of first touches sensed by the touch-sensitive screen in a period between the sensing of the control touch and the sensing of the release of the control touch; and (4) the at least one computer processor using the number of first touches to represent a value in an authentication code.Type: ApplicationFiled: March 23, 2018Publication date: September 26, 2019Inventors: Chih-Chang Lin, Chan He Lin
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Publication number: 20190273500Abstract: An edge detector includes an output node selectively coupled to a first voltage node through a first transistor, the first voltage node having a first voltage level, and a second transistor configured to continuously couple the output node to a second voltage node having a second voltage level. A capacitor includes a first terminal coupled to a gate of the first transistor and a second terminal configured to receive an input signal.Type: ApplicationFiled: May 17, 2019Publication date: September 5, 2019Inventors: Tsung-Ching (Jim) HUANG, Chan-Hong CHERN, Ming-Chieh HUANG, Chih-Chang LIN
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Patent number: 10401889Abstract: A current generator includes an amplifier having a first terminal configured to receive a first voltage, a tunable resistance circuit coupled to an output terminal of the amplifier through a first transistor, a calibration circuit coupled to the tunable resistance circuit, and a second transistor. The second transistor includes a gate terminal coupled to the output terminal of the amplifier and a drain terminal coupled to a load. The calibration circuit is configured to adjust a resistance setting of the tunable resistance circuit.Type: GrantFiled: January 6, 2016Date of Patent: September 3, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Chieh Huang, Chan-Hong Chern, Chih-Chang Lin
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Publication number: 20190253042Abstract: A clock generation circuit includes: a two-phase clock generation circuit configured to generate a first phase clock signal and a second phase clock signal based correspondingly on a non-inverted clock signal and an inverted clock signal; an inverter configured to generate the inverted clock signal based on an input clock signal; and a delay circuit which is non-inverter-based and which is configured to generate the non-inverted clock signal based on the input clock signal, the delay circuit having a predetermined delay sufficient to induce symmetry in the first and second phase clock signals such that durational midpoints of overlapping opposite phases of the first and second phase clock signals are substantially aligned.Type: ApplicationFiled: April 24, 2019Publication date: August 15, 2019Inventors: Tien-Chun YANG, Chih-Chang LIN, Ming-Chieh HUANG
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Patent number: 10367491Abstract: A delay line circuit including: a coarse-tuning arrangement, including delay units, the coarse-tuning arrangement being configured to coarsely-tune an input signal by transferring the input signal through a selected number of the delay units and thereby producing a first output signal; and a fine-tuning arrangement configured to receive the first output signal at a beginning of a signal path which includes at least three serially-connected inverters, finely-tune the first output signal along the signal path, and produce a second output signal at an end of the signal path; the fine-tuning arrangement including: a speed control unit which is selectively-connectable, and a switching circuit to selectively connect the speed control unit to the signal path based on a process-corner signal.Type: GrantFiled: June 11, 2018Date of Patent: July 30, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Chieh Huang, Chan-Hong Chern, Tsung-Ching (Jim) Huang, Chih-Chang Lin, Tien-Chun Yang
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Patent number: 10355682Abstract: A clock generation circuit includes: a two-phase clock generation circuit configured to generate a first phase clock signal and a second phase clock signal based correspondingly on a non-inverted clock signal and an inverted clock signal, the first phase clock signal and the second phase clock signal exhibiting non-overlapping logical high states; an inverter configured to generate the inverted clock signal based on an input clock signal; and a delay circuit which is non-inverter-based and which is configured to generate the non-inverted clock signal based on the input clock signal, the delay circuit having a predetermined delay sufficient to cause a difference between a first duration and a second duration within a clock cycle to be less than a predetermined tolerance.Type: GrantFiled: November 27, 2017Date of Patent: July 16, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tien-Chun Yang, Chih-Chang Lin, Ming-Chieh Huang
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Patent number: 10298237Abstract: A level shifting apparatus includes a first inverter configured to receive an input signal and a second inverter capacitively coupled with an output of the first inverter, the second inverter being configured to output an output signal. A transmission gate is configured to feed back the output signal to an input of the second inverter, wherein the transmission gate is configured to selectively interrupt feedback of the output signal to the input of the second inverter.Type: GrantFiled: January 12, 2018Date of Patent: May 21, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsung-Ching (Jim) Huang, Chan-Hong Chern, Ming-Chieh Huang, Chih-Chang Lin
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Publication number: 20190140645Abstract: A level-shifting circuit includes an input device configured to receive an input signal capable of switching between a reference voltage level and a first voltage level, and a set of capacitive devices paired in series with latch circuits. A first capacitive device of the set is coupled with an output of the input device, and each capacitive device and latch circuit pair is configured to upshift a corresponding received signal by an amount equal to a difference between the first voltage level and the reference voltage level.Type: ApplicationFiled: January 7, 2019Publication date: May 9, 2019Inventors: Chan-Hong CHERN, Tsung-Ching HUANG, Chih-Chang LIN, Ming-Chieh HUANG, Fu-Lung HSUEH