Patents by Inventor Chih-Chao CHOU

Chih-Chao CHOU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250046700
    Abstract: A method includes forming a first device die and a second device die. The first device die includes a first integrated circuit, and a first bond pad at a first surface of the first device die. The first integrated circuit is electrically connected to the first bond pad. The second device die includes a power switch that includes a first source/drain region, a second source/drain region, a second bond pad electrically connecting to the first source/drain region, and a third bond pad electrically connecting to the second source/drain region. The method further includes bonding the first device die with the second device die to form a package, with the first bond pad bonding to the third bond pad, and bonding the package to a package component.
    Type: Application
    Filed: October 26, 2023
    Publication date: February 6, 2025
    Inventors: Chih-Chao Chou, Cheng-Chi Chuang, Ching-Wei Tsai, Shang-Wen Chang
  • Patent number: 12198986
    Abstract: A semiconductor structure includes a fin disposed on a substrate, the fin including a channel region comprising a plurality of channels vertically stacked over one another, the channels comprising germanium distributed therein. The semiconductor structure further includes a gate stack engaging the channel region of the fin and gate spacers disposed between the gate stack and the source and drain regions of the fin, wherein each channel of the channels includes a middle section wrapped around by the gate stack and two end sections engaged by the gate spacers, wherein a concentration of germanium in the middle section of the channel is higher than a concentration of germanium in the two end sections of the channel, and wherein the middle section of the channel further includes a core portion and an outer portion surrounding the core portion with a germanium concentration profile from the core portion to the outer portion.
    Type: Grant
    Filed: August 7, 2023
    Date of Patent: January 14, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Sheng Yun, Chih-Hao Wang, Jui-Chien Huang, Kuo-Cheng Chiang, Chih-Chao Chou, Chun-Hsiung Lin, Pei-Hsun Wang
  • Patent number: 12183678
    Abstract: Nanostructure field-effect transistors (nano-FETs) including isolation layers formed between epitaxial source/drain regions and semiconductor substrates and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a power rail, a dielectric layer over the power rail, a first channel region over the dielectric layer, a second channel region over the first channel region, a gate stack over the first channel region and the second channel region, where the gate stack is further disposed between the first channel region and the second channel region and a first source/drain region adjacent the gate stack and electrically connected to the power rail.
    Type: Grant
    Filed: November 1, 2023
    Date of Patent: December 31, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Chiang, Shi Ning Ju, Chih-Chao Chou, Wen-Ting Lan, Chih-Hao Wang
  • Publication number: 20240404881
    Abstract: A semiconductor device structure and methods of forming the same are described. In some embodiments, the method includes depositing an etch stop layer on a substrate, depositing a first substrate layer on the etch stop layer, forming a plurality of active devices on the first substrate layer, forming an interconnection structure over the active devices, flipping over the substrate, removing the substrate, removing the etch stop layer to expose the first substrate layer, and forming a cooling substrate layer on the exposed first substrate layer. The cooling substrate layer has a thermal conductivity substantially greater than a thermal conductivity of the substrate.
    Type: Application
    Filed: June 3, 2023
    Publication date: December 5, 2024
    Inventors: Chih-Chao Chou, Chih-Hao Wang, Ching-Wei Tsai, Shang-Wen Chang, Yi-Hsun Chiu
  • Publication number: 20240363522
    Abstract: Semiconductor devices and methods are provided. A method according to the present disclosure includes receiving a substrate that includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer; forming a plurality of fins over the third semiconductor layer; forming a trench between two of the plurality of fins; depositing a dummy material in the trench; forming a gate structure over channel regions of the plurality of the fins; forming source/drain features over source/drain regions of the plurality of the fins; bonding the substrate on a carrier wafer; removing the first and second semiconductor layers to expose the dummy material; removing the dummy material in the trench; depositing a conductive material in the trench; and bonding the substrate to a silicon substrate such that the conductive material is in contact with the silicon substrate. The trench extends through the third semiconductor layer and has a bottom surface on the second semiconductor layer.
    Type: Application
    Filed: July 10, 2024
    Publication date: October 31, 2024
    Inventors: Chih-Chao Chou, Kuo-Cheng Chiang, Shi Ning Ju, Wen-Ting Lan, Chih-Hao Wang
  • Publication number: 20240313118
    Abstract: The present disclosure provides a semiconductor device that includes a semiconductor fin disposed over a substrate, an isolation structure at least partially surrounding the fin, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin, where an extended portion of the epitaxial S/D feature extends over the isolation structure, and a silicide layer disposed on the epitaxial S/D feature, where the silicide layer covers top, bottom, sidewall, front, and back surfaces of the extended portion of the S/D feature.
    Type: Application
    Filed: May 24, 2024
    Publication date: September 19, 2024
    Inventors: Pei-Hsun Wang, Chih-Chao Chou, Shih-Cheng Chen, Jung-Hung Chang, Jui-Chien Huang, Chun-Hsiung Lin, Chih-Hao Wang
  • Publication number: 20240274601
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a first fin structure over a base region of a semiconductor substrate. A first plurality of semiconductor channel structures stacked vertically with one another over the base region of the semiconductor substrate. A first width of the first fin structure is different from a second width of the first plurality of semiconductor channel structures. A gate structure extends from the first fin structure to the first plurality of semiconductor channel structures.
    Type: Application
    Filed: April 2, 2024
    Publication date: August 15, 2024
    Inventors: Chih-Chao Chou, Chih-Hao Wang, Shi Ning Ju, Kuo-Cheng Chiang, Wen-Ting Lan
  • Publication number: 20240266340
    Abstract: A package structure and a formation method are provided. The method includes disposing a first chip structure over a carrier substrate. The first chip structure has a front-side interconnection structure facing the carrier substrate. The method also includes forming a back-side interconnection structure over the first chip structure. The first chip structure has a device portion between the back-side interconnection structure and the front-side interconnection structure. The back-side interconnection structure has stacked conductive vias. The method further includes bonding a second chip structure to the first chip structure using dielectric-to-dielectric bonding and metal-to-metal bonding.
    Type: Application
    Filed: February 2, 2023
    Publication date: August 8, 2024
    Inventors: Chih-Chao CHOU, Yi-Hsun CHIU, Shang-Wen CHANG, Ching-Wei TSAI, Chih-Hao WANG
  • Patent number: 12057385
    Abstract: Semiconductor devices and methods are provided. A method according to the present disclosure includes receiving a substrate that includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer; forming a plurality of fins over the third semiconductor layer; forming a trench between two of the plurality of fins; depositing a dummy material in the trench; forming a gate structure over channel regions of the plurality of the fins; forming source/drain features over source/drain regions of the plurality of the fins; bonding the substrate on a carrier wafer; removing the first and second semiconductor layers to expose the dummy material; removing the dummy material in the trench; depositing a conductive material in the trench; and bonding the substrate to a silicon substrate such that the conductive material is in contact with the silicon substrate. The trench extends through the third semiconductor layer and has a bottom surface on the second semiconductor layer.
    Type: Grant
    Filed: July 27, 2023
    Date of Patent: August 6, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Chao Chou, Kuo-Cheng Chiang, Shi Ning Ju, Wen-Ting Lan, Chih-Hao Wang
  • Publication number: 20240250141
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a dielectric layer formed over a conductive feature; a semiconductor stack formed over the dielectric layer, wherein the semiconductor stack including semiconductor layers stacked up and separated from each other; a first metal gate structure and a second metal gate structure formed over a channel region of the semiconductor stack, wherein the first metal gate structure and the second metal gate structure wrap each of the semiconductor layers of the semiconductor stack; and a first epitaxial feature disposed between the first metal gate structure and the second metal gate structure over a first source/drain region of the semiconductor stack, wherein the first epitaxial feature extends through the dielectric layer and contacts the conductive feature.
    Type: Application
    Filed: February 27, 2024
    Publication date: July 25, 2024
    Inventors: Chih-Chao Chou, Kuo-Cheng Chiang, Shi Ning Ju, Wen-Ting Lan, Chih-Hao Wang
  • Patent number: 11996483
    Abstract: The present disclosure provides a semiconductor device that includes a semiconductor fin disposed over a substrate, an isolation structure at least partially surrounding the fin, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin, where an extended portion of the epitaxial S/D feature extends over the isolation structure, and a silicide layer disposed on the epitaxial S/D feature, where the silicide layer covers top, bottom, sidewall, front, and back surfaces of the extended portion of the S/D feature.
    Type: Grant
    Filed: December 14, 2022
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pei-Hsun Wang, Chih-Chao Chou, Shih-Cheng Chen, Jung-Hung Chang, Jui-Chien Huang, Chun-Hsiung Lin, Chih-Hao Wang
  • Patent number: 11973079
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes forming a stack of semiconductor layers comprising a plurality of first semiconductor layers and a plurality of second semiconductor layers over a semiconductor substrate. A first stack of masking layers is formed over the stack of semiconductor layers with a first width and a second stack of masking layers is formed laterally offset from the stack of semiconductor layers with a second width less than the first width. A patterning process is performed on the semiconductor substrate and the stack of semiconductor layers, thereby defining a first fin structure laterally adjacent to a second fin structure. The first fin structure has the first width and the second fin structure has the second width. The stack of semiconductor layers directly overlies the first fin structure and has the first width.
    Type: Grant
    Filed: May 19, 2022
    Date of Patent: April 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chao Chou, Chih-Hao Wang, Shi Ning Ju, Kuo-Cheng Chiang, Wen-Ting Lan
  • Patent number: 11916125
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a dielectric layer formed over a conductive feature; a semiconductor stack formed over the dielectric layer, wherein the semiconductor stack including semiconductor layers stacked up and separated from each other; a first metal gate structure and a second metal gate structure formed over a channel region of the semiconductor stack, wherein the first metal gate structure and the second metal gate structure wrap each of the semiconductor layers of the semiconductor stack; and a first epitaxial feature disposed between the first metal gate structure and the second metal gate structure over a first source/drain region of the semiconductor stack, wherein the first epitaxial feature extends through the dielectric layer and contacts the conductive feature.
    Type: Grant
    Filed: July 22, 2022
    Date of Patent: February 27, 2024
    Inventors: Chih-Chao Chou, Kuo-Cheng Chiang, Shi Ning Ju, Wen-Ting Lan, Chih-Hao Wang
  • Publication number: 20240063125
    Abstract: Nanostructure field-effect transistors (nano-FETs) including isolation layers formed between epitaxial source/drain regions and semiconductor substrates and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a power rail, a dielectric layer over the power rail, a first channel region over the dielectric layer, a second channel region over the first channel region, a gate stack over the first channel region and the second channel region, where the gate stack is further disposed between the first channel region and the second channel region and a first source/drain region adjacent the gate stack and electrically connected to the power rail.
    Type: Application
    Filed: November 1, 2023
    Publication date: February 22, 2024
    Inventors: Kuo-Cheng Chiang, Shi Ning Ju, Chih-Chao Chou, Wen-Ting Lan, Chih-Hao Wang
  • Patent number: 11855178
    Abstract: A semiconductor device is provided. The semiconductor device includes a fin protruding from a semiconductor substrate and a gate structure formed across the fin. The semiconductor device also includes a gate spacer formed over a sidewall of the gate structure. The gate spacer includes a sidewall spacer and a sealing spacer formed above the sidewall spacer. In addition, an air gap is vertically sandwiched between the sidewall spacer and the sealing spacer. The semiconductor device further includes a hard mask formed over the gate structure and covering a sidewall of the sealing spacer.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Hsiung Lin, Pei-Hsun Wang, Chih-Chao Chou, Chia-Hao Chang, Chih-Hao Wang
  • Patent number: 11842965
    Abstract: Nanostructure field-effect transistors (nano-FETs) including isolation layers formed between epitaxial source/drain regions and semiconductor substrates and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a power rail, a dielectric layer over the power rail, a first channel region over the dielectric layer, a second channel region over the first channel region, a gate stack over the first channel region and the second channel region, where the gate stack is further disposed between the first channel region and the second channel region and a first source/drain region adjacent the gate stack and electrically connected to the power rail.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: December 12, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Chiang, Shi Ning Ju, Chih-Chao Chou, Wen-Ting Lan, Chih-Hao Wang
  • Publication number: 20230386936
    Abstract: A semiconductor structure includes a fin disposed on a substrate, the fin including a channel region comprising a plurality of channels vertically stacked over one another, the channels comprising germanium distributed therein. The semiconductor structure further includes a gate stack engaging the channel region of the fin and gate spacers disposed between the gate stack and the source and drain regions of the fin, wherein each channel of the channels includes a middle section wrapped around by the gate stack and two end sections engaged by the gate spacers, wherein a concentration of germanium in the middle section of the channel is higher than a concentration of germanium in the two end sections of the channel, and wherein the middle section of the channel further includes a core portion and an outer portion surrounding the core portion with a germanium concentration profile from the core portion to the outer portion.
    Type: Application
    Filed: August 7, 2023
    Publication date: November 30, 2023
    Inventors: Wei-Sheng Yun, Chih-Hao Wang, Jui-Chien Huang, Kuo-Cheng Chiang, Chih-Chao Chou, Chun-Hsiung Lin, Pei-Hsun Wang
  • Publication number: 20230369196
    Abstract: Semiconductor devices and methods are provided. A method according to the present disclosure includes receiving a substrate that includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer; forming a plurality of fins over the third semiconductor layer; forming a trench between two of the plurality of fins; depositing a dummy material in the trench; forming a gate structure over channel regions of the plurality of the fins; forming source/drain features over source/drain regions of the plurality of the fins; bonding the substrate on a carrier wafer; removing the first and second semiconductor layers to expose the dummy material; removing the dummy material in the trench; depositing a conductive material in the trench; and bonding the substrate to a silicon substrate such that the conductive material is in contact with the silicon substrate. The trench extends through the third semiconductor layer and has a bottom surface on the second semiconductor layer.
    Type: Application
    Filed: July 27, 2023
    Publication date: November 16, 2023
    Inventors: Chih-Chao Chou, Kuo-Cheng Chiang, Shi Ning Ju, Wen-Ting Lan, Chih-Hao Wang
  • Patent number: 11776854
    Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor device includes a fin protruding from a substrate and an isolation structure surrounding the fin. The semiconductor device also includes a first channel layer and a second channel layer formed over the fin and at least partially overlapping the isolation structure. The semiconductor device further includes a gate structure formed in a space between the first channel layer and the second channel layer and wrapping around the first channel layer and the second channel layer.
    Type: Grant
    Filed: May 27, 2022
    Date of Patent: October 3, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Pei-Hsun Wang, Chun-Hsiung Lin, Chih-Hao Wang, Chih-Chao Chou
  • Patent number: 11742280
    Abstract: Semiconductor devices and methods are provided. A method according to the present disclosure includes receiving a substrate that includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer; forming a plurality of fins over the third semiconductor layer; forming a trench between two of the plurality of fins; depositing a dummy material in the trench; forming a gate structure over channel regions of the plurality of the fins; forming source/drain features over source/drain regions of the plurality of the fins; bonding the substrate on a carrier wafer; removing the first and second semiconductor layers to expose the dummy material; removing the dummy material in the trench; depositing a conductive material in the trench; and bonding the substrate to a silicon substrate such that the conductive material is in contact with the silicon substrate. The trench extends through the third semiconductor layer and has a bottom surface on the second semiconductor layer.
    Type: Grant
    Filed: July 8, 2022
    Date of Patent: August 29, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Chao Chou, Kuo-Cheng Chiang, Shi Ning Ju, Wen-Ting Lan, Chih-Hao Wang