Abstract: A wafer container includes a frame, a door and at least a pair of shelves. The frame has opposite sidewalls. The pair of the shelves are respectively disposed and aligned on the opposite sidewalls of the frame. Various methods and devices are provided for holding at least one wafer to the shelves during transport.

Abstract: A package structure, including a circuit board, multiple circuit structure layers, at least one bridge structure, and at least one supporting structure, is provided. The circuit structure layer is disposed on the circuit board. The bridge structure is connected between the two adjacent circuit structure layers. The supporting structure is located between the two adjacent circuit structure layers, and the supporting structure has a first end and a second end opposite to each other and respectively connecting the bridge structure and the circuit board.

Abstract: A memory device includes a plurality of word lines elongated along a first direction, and at least one memory unit. The at least one memory unit includes a plurality of memory cells, at least one bit line, and at least one column word line. The plurality of memory cells are arranged along a second direction different from the first direction. The at least one bit line is elongated along the second direction, and configured to transmit data of a selected memory cell. The at least one column word line is elongated along the second direction, and configured to control electrical connections between the memory cells and the at least one bit line, wherein the selected memory cell is selected by a corresponding word line and the at least one column word line.

Abstract: A memory device includes a plurality of word lines elongated along a first direction, and at least one memory unit. The at least one memory unit includes a plurality of memory cells, at least one bit line, and at least one column word line. The plurality of memory cells are arranged along a second direction different from the first direction. The at least one bit line is elongated along the second direction, and configured to transmit data of a selected memory cell. The at least one column word line is elongated along the second direction, and configured to control electrical connections between the memory cells and the at least one bit line, wherein the selected memory cell is selected by a corresponding word line and the at least one column word line.

Abstract: The present invention provides a memory device. The memory device comprises a plurality of word lines; and at least one memory unit comprising a plurality of memory cell groups; at least one bit line; a plurality of local bit lines; a column word line elongated along the second direction; and a plurality of column switches, each of the column switches configured to control conduction between the at least one bit line and one of the local bit lines; wherein a plurality of the memory units are arranged along the first direction, a number of the memory units form a memory block, and the column word lines of the memory units are grouped to control the column switches of corresponding memory blocks respectively.

Abstract: A memory device includes a plurality of word lines elongated along a first direction, and at least one memory unit. The at least one memory unit includes a plurality of memory cells, at least one bit line, and at least one column word line. The plurality of memory cells are arranged along a second direction different from the first direction. The at least one bit line is elongated along the second direction, and configured to transmit data of a selected memory cell. The at least one column word line is elongated along the second direction, and configured to control electrical connections between the memory cells and the at least one bit line, wherein the selected memory cell is selected by a corresponding word line and the at least one column word line.

Abstract: A memory device includes a plurality of word lines elongated along a first direction, and at least one memory unit. The at least one memory unit includes a plurality of memory cells, at least one bit line, and at least one column word line. The plurality of memory cells are arranged along a second direction different from the first direction. The at least one bit line is elongated along the second direction, and configured to transmit data of a selected memory cell. The at least one column word line is elongated along the second direction, and configured to control electrical connections between the memory cells and the at least one bit line, wherein the selected memory cell is selected by a corresponding word line and the at least one column word line.

Abstract: A memory device includes a plurality of word lines elongated along a first direction, and at least one memory unit. The at least one memory unit includes a plurality of memory cells, at least one bit line, and at least one column word line. The plurality of memory cells are arranged along a second direction different from the first direction. The at least one bit line is elongated along the second direction, and configured to transmit data of a selected memory cell. The at least one column word line is elongated along the second direction, and configured to control electrical connections between the memory cells and the at least one bit line, wherein the selected memory cell is selected by a corresponding word line and the at least one column word line.

Abstract: A memory device comprises a plurality of word lines elongated along a first direction, and at least one memory unit. The at least one memory unit comprises a plurality of memory cells arranged along a second direction different from the first direction; at least one bit line elongated along the second direction, and configured to transmit data of a selected memory cell; and at least one column word line elongated along the second direction; wherein the memory cell comprises a storage cell configured to store data and at least two access transistors; wherein a control terminal of one of the at least two access transistors of the memory cell is coupled to the at least one column word line, and a control terminal of another one of the at least two access transistors of the memory cell is coupled to the corresponding word line.

Abstract: A photolithography system includes a photo-mask storage, at least one photolithography machine and an overhead crane for transporting at least one photo-mask at least between the photo-mask storage and the photolithography machine. The overhead crane includes at least one main rail, a mask girder, a mask hoist and a mask holding device. The mask girder is coupled with the main rail and movable at least between a first position above the photo-mask storage and a second position above the photolithography machine. The mask hoist is movably coupled with the mask girder. The mask holding device is coupled with the mask hoist.

Abstract: A memory device comprises a plurality of word lines elongated along a first direction, and at least one memory unit. The at least one memory unit comprises a plurality of memory cells arranged along a second direction different from the first direction; at least one bit line elongated along the second direction, and configured to transmit data of a selected memory cell; and at least one column word line elongated along the second direction; wherein the memory cell comprises a storage cell configured to store data and at least two access transistors; wherein a control terminal of one of the at least two access transistors of the memory cell is coupled to the at least one column word line, and a control terminal of another one of the at least two access transistors of the memory cell is coupled to the corresponding word line.

Abstract: A memory device includes a plurality of memory modules and a plurality of control lines. Each memory module includes a plurality of memory units. Each memory unit includes: a plurality of memory cell groups, each of which includes at least one memory cell; a plurality of first bit lines, each of which is coupled to the at least one memory cell of a respective memory cell group; a second bit line; and a plurality of controllable circuits, each of which has an input terminal coupled to a respective first bit line, an output terminal coupled to the second bit line, and a control terminal. Each control line is coupled to the control terminal of a corresponding controllable circuit of each of at least one memory unit of each memory module. The memory device consumes relatively small power.

Abstract: A memory device includes a plurality of memory modules and a plurality of control lines. Each memory module includes a plurality of memory units. Each memory unit includes: a plurality of memory cell groups, each of which includes at least one memory cell; a plurality of first bit lines, each of which is coupled to the at least one memory cell of a respective memory cell group; a second bit line; and a plurality of controllable circuits, each of which has an input terminal coupled to a respective first bit line, an output terminal coupled to the second bit line, and a control terminal. Each control line is coupled to the control terminal of a corresponding controllable circuit of each of at least one memory unit of each memory module. The memory device consumes relatively small power.

Abstract: An SRAM cell includes a write inverter including a write pull-up transistor and a write pull-down transistor, a read inverter including a read pull-up transistor and a read pull-down transistor, a write access transistor coupled between an output terminal of the write inverter and a write bit line, and a read access transistor coupled between an output terminal of the read inverter and a read bit line. The SRAM cell performs at least one of a first read operation and a second read operation. Wherein in the first read operation, a voltage of the read bit line is initially at a logic high voltage level, and the write pull-down transistor is not turned on. Wherein in the second read operation, the voltage of the read bit line is initially at a logic low voltage level, and the write pull-up transistor is not turned on.

Abstract: A printed circuit board precursor includes a substrate, a catalytic layer, a conductive layer, and a metal layer. The substrate has a top surface, a bottom surface, and a wall defining a channel, and the channel completely penetrates through the substrate from the top surface to the bottom surface. The catalytic layer is formed on the top surface, the bottom surface, and the wall of the substrate. The conductive layer is attached to and covers the catalytic layer. The metal layer is disposed on the conductive layers and filled in the channel.

Abstract: A memory device includes a memory cell unit, a bit line unit and a buffering unit. The memory cell unit includes a plurality of memory cell groups. Each memory cell group includes at least one memory cell for storing data therein. The bit line unit includes a plurality of first bit lines each coupled to the at least one memory cell of a respective memory cell group, and a second bit line for transmitting to-be-read data. The buffering unit includes a plurality of two-state buffers. Each two-state buffer has an input terminal coupled to a respective first bit line, and an output terminal coupled to the second bit line. The memory device does not require a sense amplifier, and thus consumes relatively small power. The memory device can operate at a relatively high frequency when properly configured.

Abstract: A method of manufacturing a printed circuit board precursor includes the steps of providing a substrate. Then the surface of the substrate is catalyzed to form a catalytic layer by a catalyst. Subsequently, a conductive layer is formed and attached to the surface of the catalytic layer. Finally, a metal layer is electroplated on the conductive layer. A printed circuit board precursor includes a substrate having a surface. Specifically, the surface is catalytically treated to form a catalytic layer. The precursor also includes a conductive layer which is attached to and covers the catalytic layer and a metal layer which is disposed on the conductive layer.

Abstract: A memory device includes a plurality of word lines elongated along a first direction, and at least one memory unit. The at least one memory unit includes a plurality of memory cells, at least one bit line, and at least one column word line. The plurality of memory cells are arranged along a second direction different from the first direction. The at least one bit line is elongated along the second direction, and configured to transmit data of a selected memory cell. The at least one column word line is elongated along the second direction, and configured to control electrical connections between the memory cells and the at least one bit line, wherein the selected memory cell is selected by a corresponding word line and the at least one column word line.

Abstract: A memory device includes a memory cell unit, a bit line unit and a buffering unit. The memory cell unit includes a plurality of memory cell groups. Each memory cell group includes at least one memory cell for storing data therein. The bit line unit includes a plurality of first bit lines each coupled to the at least one memory cell of a respective memory cell group, and a second bit line for transmitting to-be-read data. The buffering unit includes a plurality of two-state buffers. Each two-state buffer has an input terminal coupled to a respective first bit line, and an output terminal coupled to the second bit line. The memory device does not require a sense amplifier, and thus consumes relatively small power. The memory device can operate at a relatively high frequency when properly configured.

Abstract: A flexible circuit board comprises a substrate which has a polyimide layer recessed to define at least a compartment. The compartment includes an inner wall surface having a side wall and a bottom wall. The compartment is for containing a multilayer unit, wherein the multilayer unit includes an adhesion enhancing layer formed on the wall of the compartment, a first electrically conducting layer disposed on the adhesion enhancing layer, and a second electrically conducting layer formed on the first electrically conducting layer. The adhesion enhancing layer is palladium. The first electrically conducting layer is nickel. The substrate is composed of polyimide (PI).