LOW POWER MEMORY DEVICE WITH COLUMN AND ROW LINE SWITCHES FOR SPECIFIC MEMORY CELLS
The present invention provides a memory device. The memory device comprises a plurality of word lines; and at least one memory unit comprising a plurality of memory cell groups; at least one bit line; a plurality of local bit lines; a column word line elongated along the second direction; and a plurality of column switches, each of the column switches configured to control conduction between the at least one bit line and one of the local bit lines; wherein a plurality of the memory units are arranged along the first direction, a number of the memory units form a memory block, and the column word lines of the memory units are grouped to control the column switches of corresponding memory blocks respectively.
This application is a continuation application of U.S. application Ser. No. 15/949,077, filed on Apr. 10, 2018, which is a continuation application of U.S. application Ser. No. 14/840,037, filed on Aug. 30, 2015, the contents of which are incorporated by reference.
BACKGROUND OF THE INVENTION 1. Field of the InventionThe present invention relates to a memory device, and more particularly, to a memory device with low power consumption.
2. Description of the Prior ArtPlease refer to
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In the memory devices 100, 200, 300 of the prior art, when one of the word lines WL0-WL255 selects a corresponding row of the memory cells MC, all the bit lines BL0-BL255 are coupled to corresponding selected memory cells for the read/write operation. However, during the read/write operation, some of the bit lines BL0-BL255 are not required to transmit data. The idle bit lines consume power during the read/write operation, such that the memory device 100 of the prior art has higher power consumption.
SUMMARY OF THE INVENTIONThe present invention provides a memory device, which comprises a plurality of word lines elongated along a first direction; and at least one memory unit comprising a plurality of memory cell groups arranged along a second direction different from the first direction, each of the memory cell groups comprising a plurality of memory cells; at least one bit line elongated along the second direction, and configured to transmit data of a selected memory cell; a plurality of local bit lines, elongated along the second direction, wherein a memory cell group is coupled to a local bit line; a column word line elongated along the second direction; a plurality of row word lines elongated along the first direction; a plurality of column switches arranged along the second direction, each of the column switches having a control terminal coupled to the column word line, a first terminal, and a second terminal, each of the column switches configured to control conduction between the first terminal and the second terminal according to signals received from the control terminal; and a plurality of row switches arranged along the second direction, each of the row switches having a control terminal coupled to a row word line, a first terminal, and a second terminal, each of the row switches configured to control conduction between the first terminal and the second terminal according to signals received from the control terminal; wherein one of the column switches and one of the row switches are electrically coupled in series between the at least one bit line and one of the local bit line.
The present invention provides a memory device, which comprises a plurality of word lines elongated along a first direction; and at least one memory unit comprising a plurality of memory cell groups arranged along a second direction different from the first direction, each of the memory cell groups comprising a plurality of memory cells; at least one bit line elongated along the second direction, and configured to transmit data of a selected memory cell; a plurality of local bit lines, elongated along the second direction, wherein a memory cell group is coupled to a local bit line; a column word line elongated along the second direction; and a plurality of column switches arranged along the second direction, each of the column switches having a control terminal coupled to the at least one column word line, a first terminal coupled to one of the local bit lines, and a second terminal coupled to the at least one bit line, each of the column switches configured to control conduction between the at least one bit line and one of the local bit lines; wherein a plurality of the memory units are arranged along the first direction, a number of the memory units form a memory block, and the column word lines of the memory units are grouped to control the column switches of corresponding memory blocks respectively.
The present invention provides a memory device, which comprises a plurality of word lines elongated along a first direction; and at least one memory unit comprising a plurality of memory cell groups arranged along a second direction different from the first direction, each of the memory cell groups comprising a plurality of memory cells; at least one bit line elongated along the second direction, and configured to transmit data of a selected memory cell; a plurality of local bit lines, elongated along the second direction, wherein a memory cell group is coupled to a local bit line; a column word line elongated along the second direction; a plurality of row word lines elongated along the first direction; wherein the selected memory cell is selected by a corresponding word line, the column word line and a corresponding row word line.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
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According to the above arrangement, when one of the word lines WL0-WL255 selects a corresponding row of the memory cells MC for a read/write operation, the column word lines CWL0-CWL7 can be used to further select the memory cells MC of the specific memory block bk0-bk7 for the read/write operation. For example, when the column word line CWL0 transmits a control signal to the control terminals of the switches SW of the memory block bk0, only the switches SW of the memory block bk0 are turned on to couple the memory cells MC of the memory block bk0 to the corresponding bit lines (bit0_bk0 to bit31_bk0), for allowing the corresponding bit lines (bit0_bk0 to bit31_bk0) to transmit data. On the other hand, other bit lines corresponding to the memory block bk1-bk7 are not driven to transmit data. Therefore, the power consumption of the memory device 400a can be reduced.
In addition, the memory cell MC may correspond to a plurality of bit lines. For example, when the memory cell is a memory cell of SRAM, the memory cell may be selected to couple to two bit lines. Accordingly, two or more column word lines can be arranged to control electrical connections between the memory cell and the two bit lines.
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Similarly, when one of the word lines WL0-WL255 selects a corresponding row of the memory cells MC for the read/write operation, the column word lines CWL0-CWL7 can be used to further select the memory cells MC of the specific memory block bk0-bk7 for the read/write operation. For example, when the word line CWL0 transmits a control signal to the control terminals of the switches SW of the memory block bk0, only the switches SW of the memory block bk0 are turned on to couple the memory cells MC of the memory block bk0 to the corresponding bit lines (bit0_bk0 to bit31_bk0), for allowing the corresponding bit lines (bit0_bk0 to bit31_bk0) to transmit data. On the other hand, other bit lines corresponding to the memory block bk1-bk7 are not driven to transmit data. Therefore, the power consumption of the memory device 500a can be reduced.
Note that, in the memory device 500a in
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The second word line arrangement of
In other words, the memory unit 70 may be applied to the memory unit within the memory device 400a of
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In the embodiments of
Comparing with the first word line arrangement of
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Comparing with the first word line arrangement and the second word line arrangement, the third word line arrangement only turns on one switch SW of each column of the memory cells MC for transmitting data. Thus the third word line arrangement can further reduce power consumption of the memory device. However, a number of the row word lines (RWL0_bk0 to RWL31_bk7) is a multiple of a number of the column word lines CWL0-CWL7. The third word line arrangement may need to form the plurality of row word lines in different metal layers, but the first word line arrangement and the second word line arrangement can form the plurality of column word lines in a same metal layer. For example, when each of the memory cell group comprises four memory cells, and the memory device comprises 32 memory blocks, there are totally 32 row word lines need to be arranged within a layout area of the four memory cells for passing through. Thus the 32 row word lines must be form in different metal layers. As to the first word line arrangement and the second word line arrangement, only one column word line needs to be arranged within the layout area of the memory cells. Thus the column word lines can be formed in a same metal layer.
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According to the above arrangement, the memory device 400c can also reduce power consumption. Moreover, the memory device 400c can operate in two modes. For example, when the column word lines are configured to turn on all the column switches SW1 in default, the memory device 400c can operate similarly to the memory device 400b; and when branches of column word lines, which extend to the memory units, of each memory block are further grouped into four groups to respectively control eight columns of memory cells to work individually, the memory device 400c can operate in a byte enable mode for outputting data in byte format.
When the third word line arrangement in
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In the above embodiments, the memory cells MC are arranged into a matrix having 256 rows and 256 columns, the plurality of memory cells are divided into 8 memory blocks bk0-bk7, each of the 8 memory blocks bk0-bk7 comprises 32 columns of the memory cells MC, and each memory cell group comprises 8 memory cells. However, the present invention is not limited to the above embodiment. In other embodiment of the present invention, the numbers of rows and columns of the matrix, the number of the memory blocks in the memory device, the number of columns of the memory cells in the memory block, and the number of the memory cells in the memory cell group can be different from the above numbers and determined according to design requirements.
In contrast to the prior art, the memory device of the present invention comprises the column word lines and/or the row word lines for further selecting specific memory cells to be coupled to corresponding bit lines, such that other bit lines corresponding to the unselected memory cells are not driven to transmit data. Therefore, the memory device of the present invention has lower power consumption.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Claims
1. A memory device, comprising:
- a plurality of word lines elongated along a first direction; and
- at least one memory unit comprising: a plurality of memory cell groups arranged along a second direction different from the first direction, each of the memory cell groups comprising a plurality of memory cells; at least one bit line elongated along the second direction, and configured to transmit data of a selected memory cell; a plurality of local bit lines, elongated along the second direction, wherein a memory cell group is coupled to a local bit line; a column word line elongated along the second direction; a plurality of row word lines elongated along the first direction; a plurality of column switches arranged along the second direction, each of the column switches having a control terminal coupled to the column word line, a first terminal, and a second terminal, each of the column switches configured to control conduction between the first terminal and the second terminal according to signals received from the control terminal; and a plurality of row switches arranged along the second direction, each of the row switches having a control terminal coupled to a row word line, a first terminal, and a second terminal, each of the row switches configured to control conduction between the first terminal and the second terminal according to signals received from the control terminal; wherein one of the column switches and one of the row switches are electrically coupled in series between the at least one bit line and one of the local bit line.
2. The memory device of claim 1, wherein the selected memory cell is selected by a corresponding word line, the at least one column word line and a corresponding row word line.
3. The memory device of claim 1, wherein the plurality of column switches and the plurality of row switches are transistors.
4. The memory device of claim 1, wherein the memory device comprises a plurality of the memory units arranged along the first direction, a predetermined number of the memory units form a memory block, and the column word lines of the memory units are grouped to control the column switches of corresponding memory blocks respectively.
5. The memory device of claim 1, wherein in the at least one memory unit, the plurality of memory cell groups arranged along the second direction are electrically isolated from each other by the plurality of row switches.
6. The memory device of claim 1, wherein the memory device comprises a plurality memory blocks arranged along the first direction, each memory block comprises a plurality of memory units arranged along the first direction, the plurality memory blocks receive a plurality of column word line signals, respectively, and column switches within a first memory block are controlled by a first column word line signal among the plurality of column word line signals.
7. The memory device of claim 6, wherein a plurality of second memory units within a second memory block and a plurality of third memory units within a third memory block are disposed in an interleaved manner.
8. A memory device, comprising:
- a plurality of word lines elongated along a first direction; and
- at least one memory unit comprising: a plurality of memory cell groups arranged along a second direction different from the first direction, each of the memory cell groups comprising a plurality of memory cells; at least one bit line elongated along the second direction, and configured to transmit data of a selected memory cell; a plurality of local bit lines, elongated along the second direction, wherein a memory cell group is coupled to a local bit line; a column word line elongated along the second direction; and a plurality of column switches arranged along the second direction, each of the column switches having a control terminal coupled to the column word line, a first terminal coupled to one of the local bit lines, and a second terminal coupled to the at least one bit line, each of the column switches configured to control conduction between the at least one bit line and one of the local bit lines;
- wherein a plurality of the memory units are arranged along the first direction, a number of the memory units form a memory block, and the column word lines of the memory units are grouped to control the column switches of corresponding memory blocks respectively.
9. The memory device of claim 8, wherein the selected memory cell is selected by a corresponding word line, the at least one column word line and a corresponding row word line.
10. The memory device of claim 8, wherein the plurality of column switches and the plurality of row switches are transistors.
11. The memory device of claim 8, wherein the at least one memory unit further comprises:
- a plurality of row word lines elongated along the first direction; and
- a plurality of row switches arranged along the second direction, each of the row switches having a control terminal coupled to a corresponding row word line;
- wherein each of the row switches and a corresponding column switch are coupled between one of the memory cell groups and the at least one bit line in series;
- wherein in the at least one memory unit, the plurality of memory cell groups arranged along the second direction are electrically isolated from each other by the plurality of row switches.
12. The memory device of claim 8, wherein the memory device comprises a plurality memory blocks arranged along the first direction, each memory block comprises a plurality of memory units arranged along the first direction, the plurality memory blocks receive a plurality of column word line signals, respectively, and column switches within a first memory block are controlled by a first column word line signal among the plurality of column word line signals.
13. The memory device of claim 8, wherein a plurality of second memory units within a second memory block and a plurality of third memory units within a third memory block are disposed in an interleaved manner.
14. A memory device, comprising:
- a plurality of word lines elongated along a first direction; and
- at least one memory unit comprising: a plurality of memory cell groups arranged along a second direction different from the first direction, each of the memory cell groups comprising a plurality of memory cells; at least one bit line elongated along the second direction, and configured to transmit data of a selected memory cell; a plurality of local bit lines, elongated along the second direction, wherein a memory cell group is coupled to a local bit line; a column word line elongated along the second direction; and a plurality of row word lines elongated along the first direction;
- wherein the selected memory cell is selected by a corresponding word line, the column word line and a corresponding row word line.
15. The memory device of claim 14, wherein the memory device comprises a plurality memory blocks arranged along the first direction, each memory block comprises a plurality of memory units arranged along the first direction, the plurality memory blocks receive a plurality of column word line signals, respectively, and column switches within a first memory block are controlled by a first column word line signal among the plurality of column word line signals.
16. The memory device of claim 14, wherein a plurality of second memory units within a second memory block and a plurality of third memory units within a third memory block are disposed in an interleaved manner.
Type: Application
Filed: Feb 26, 2020
Publication Date: Jun 18, 2020
Inventor: Chih-Cheng Hsiao (Taichung City)
Application Number: 16/801,164