Patents by Inventor Chih-Cheng Hsieh

Chih-Cheng Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8704580
    Abstract: The present invention discloses a circuit sharing time delay integrator structure. The major composing elements of this circuit sharing time delay integrator structure are: a sharing circuit, a first control block, a plurality of second control blocks and a timing set generated by a timing generator circuit. The sharing circuit can be an OP-AMP, an active load, or any of a variety of combinations used in signal accumulation applications. With the implementation of the present invention to applications of signal accumulations, the necessity of an adder circuitry is eliminated, the overall circuitry and hence the total amount of transistors required when producing the integrated circuit is massively reduced, and thus a great cost reduction and better timing and power efficiency can all be thereof achieved.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: April 22, 2014
    Assignee: National Applied Research Laboratories
    Inventors: Chin-Fong Chiu, Hann-Huei Tsai, Wen-Hsu Chang, Chih-Cheng Hsieh, Kuo-Wei Cheng
  • Publication number: 20140084136
    Abstract: The present invention is related to an optical recognition system and a method thereof, and more particularly to an optical recognition system and a method that adopts a single-slope analog-to-digital converter to proceed a single-slope analog-to-digital conversion in order to have an image with a wide dynamic range.
    Type: Application
    Filed: September 27, 2012
    Publication date: March 27, 2014
    Applicant: NATIONAL TSING HUA UNIVERSITY
    Inventors: Chih-Cheng Hsieh, Shang-Fu Yeh, Chun-Kai Liu, Chiao-Jen Cheng
  • Publication number: 20130335132
    Abstract: The present invention discloses a circuit sharing time delay integrator structure. The major composing elements of this circuit sharing time delay integrator structure are: a sharing circuit, a first control block, a plurality of second control blocks and a timing set generated by a timing generator circuit. The sharing circuit can be an OP-AMP, an active load, or any of a variety of combinations used in signal accumulation applications. With the implementation of the present invention to applications of signal accumulations, the necessity of an adder circuitry is eliminated, the overall circuitry and hence the total amount of transistors required when producing the integrated circuit is massively reduced, and thus a great cost reduction and better timing and power efficiency can all be thereof achieved.
    Type: Application
    Filed: August 24, 2012
    Publication date: December 19, 2013
    Applicant: National Applied Research Laboratories
    Inventors: Chin-Fong CHIU, Hann-Huei TSAI, Wen-Hsu CHANG, Chih-Cheng HSIEH, Kuo-Wei CHENG
  • Publication number: 20130313696
    Abstract: A power semiconductor package and a method of method of manufacturing the same are disclosed, where the power semiconductor package includes a lead frame, a first die, a second die and a single connecting strip. The lead frame includes a voltage plate, a grounding plate, an output plate, a first gate plate and a second gate plate. The first die is disposed on the voltage plate, and a high side transistor within the first die is connected to the first gate plate. The second die is disposed on the grounding plate, and a low side transistor within the second die is connected to the second gate plate. The connecting strip is disposed on the first and second dies and the output plate and electrically connects to a source of the high side transistor and a drain of the low side transistor.
    Type: Application
    Filed: November 22, 2012
    Publication date: November 28, 2013
    Applicant: NIKO SEMICONDUCTOR CO., LTD.
    Inventors: Chih-Cheng HSIEH, Chung-Ming LENG
  • Publication number: 20130265066
    Abstract: A pixel array module with a self-test function including a test circuit unit, a plurality of test lines, and a pixel array is provided. The test circuit unit provides the self-test function. The test lines are connected between the test circuit unit and the pixel array. The pixel array is connected to the test circuit unit through the test lines and includes a plurality of pixels. Each pixel includes a transistor. Each transistor has a first terminal and a second terminal. Regarding each of the pixels, a driving signal of the transistor is transmitted from the first terminal to the second terminal thereof under a normal mode, and a test signal of the transistor is transmitted from the second terminal to the first terminal thereof under a test mode. Furthermore, a self-test method of the foregoing pixel array module is also provided.
    Type: Application
    Filed: July 1, 2012
    Publication date: October 10, 2013
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chih-Cheng Hsieh, Shang-Fu Yeh, Ka-Yi Yeh
  • Publication number: 20120205520
    Abstract: An image sensor including a pixel array is provided. The pixel array includes R×S sub-pixel arrays. The sub-pixel array includes P×Q pixels. Each pixel includes a photodiode, a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor. The gate of the second transistor is coupled to a row control signal. The second source/drain electrode of the second transistor is coupled to a column control signal. The gate electrode of the third transistor is coupled to a reset signal. The second source/drain electrode of the third transistor is coupled to a column voltage reset signal. The gate electrode of the fifth transistor is coupled to a row select signal. The sub-pixel array uses the row control signal, the column control signal, the column voltage reset signal, and the row select signal to select an output the sensing signal of one of the pixels.
    Type: Application
    Filed: April 13, 2011
    Publication date: August 16, 2012
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chih-Cheng Hsieh, Shang-Fu Yeh, Ka-Yi Yeh
  • Publication number: 20120193775
    Abstract: A semiconductor structure comprising a semiconductor unit, a first conductive structure, a first conductive plug, and a second conductive structure is provided. The semiconductor unit has a substrate on a first side of the semiconductor unit. The substrate has at least a hole. The first conductive plug is in the hole and the hole may be full of the conductive plug. The first conductive structure is on the surface of the semiconductor unit. The surface is at the first side of the semiconductor unit. The second conductive structure is on a surface at a second side of the substrate of the semiconductor unit.
    Type: Application
    Filed: November 29, 2011
    Publication date: August 2, 2012
    Applicant: NIKO SEMICONDUCTOR CO., LTD.
    Inventors: HSIU WEN HSU, CHIH CHENG HSIEH
  • Patent number: 7705367
    Abstract: A pinned photodiode sensor with gate-controlled SCR switch includes a pinned photodiode and a gate-controlled SCR switch. The SCR switch includes a P-type substrate, an N? doped region, and an N+ doped region formed on the substrate; a P+ doped region formed on the N? doped region; an oxide layer formed on the P substrate, the N? doped region, the N+ doped region, and the P+ doped region; and a gate formed above the P substrate and the N? doped region. The gate includes a P+ doped region and an N+ doped region. During an exposure procedure, a depletion region will not reach the interface between the oxide layer and the substrate, thereby preventing dark current leakage.
    Type: Grant
    Filed: May 4, 2006
    Date of Patent: April 27, 2010
    Assignee: PixArt Imaging Inc.
    Inventors: Chien-Chang Huang, Chih-Cheng Hsieh, Ching-Wei Chen
  • Patent number: 7436011
    Abstract: A CMOS image sensor includes a semiconductor substrate; a pinned photodiode formed in a light-sensing region of the semiconductor substrate, the pinned photodiode comprising a charge-accumulating diffusion region and a surface pinning diffusion region overlying the charge-accumulating diffusion region; a transfer transistor, wherein the transfer transistor has a transfer gate comprising a protruding first gate segment with a first gate dimension and a second gate segment with a second gate dimension that is smaller than the first gate dimension. A first overlapping portion between the protruding first gate segment and the charge-accumulating diffusion region is greater than a second overlapping portion between the second gate segment and the charge-accumulating diffusion region.
    Type: Grant
    Filed: November 10, 2005
    Date of Patent: October 14, 2008
    Assignee: PixArt Imaging Inc.
    Inventors: Ching-Wei Chen, Chih-Cheng Hsieh, Chien-Chang Huang
  • Patent number: 7323378
    Abstract: This invention provides a CMOS image sensor having a pinned photodiode. A P substrate is provided having thereon a P well. The P well is adjacent to a light-sensing region of the CMOS image sensor. A gate electrode of a transfer transistor of the CMOS image sensor is formed on the P well. A self-aligned implantation is performed to form N-type diode diffusion within the light-sensing region. An oblique ion implantation process is then performed to form N-type pocket diffusion directly under the gate electrode. Spacers are formed on sidewalls of the gate electrode. A surface P+ pinning diffusion region is then formed in the diode diffusion region.
    Type: Grant
    Filed: October 20, 2005
    Date of Patent: January 29, 2008
    Assignee: PixArt Imaging Inc.
    Inventors: Ching-Wei Chen, Chih-Cheng Hsieh, Chien-Chang Huang
  • Publication number: 20070280313
    Abstract: A method for driving a light emitting device includes providing a first current source coupled to an input terminal of the light emitting device, and providing a second current source coupled to an output terminal of the light emitting device.
    Type: Application
    Filed: June 6, 2006
    Publication date: December 6, 2007
    Inventors: Chih-Cheng Hsieh, Sheng-Yeh Lai
  • Publication number: 20070102739
    Abstract: A CMOS image sensor includes a semiconductor substrate; a pinned photodiode formed in a light-sensing region of the semiconductor substrate, the pinned photodiode comprising a charge-accumulating diffusion region and a surface pinning diffusion region overlying the charge-accumulating diffusion region; a transfer transistor, wherein the transfer transistor has a transfer gate comprising a protruding first gate segment with a first gate dimension and a second gate segment with a second gate dimension that is smaller than the first gate dimension. A first overlapping portion between the protruding first gate segment and the charge-accumulating diffusion region is greater than a second overlapping portion between the second gate segment and the charge-accumulating diffusion region.
    Type: Application
    Filed: November 10, 2005
    Publication date: May 10, 2007
    Inventors: Ching-Wei Chen, Chih-Cheng Hsieh, Chien-Chang Huang
  • Publication number: 20070092986
    Abstract: This invention provides a CMOS image sensor having a pinned photodiode. A P substrate is provided having thereon a P well. The P well is adjacent to a light-sensing region of the CMOS image sensor. A gate electrode of a transfer transistor of the CMOS image sensor is formed on the P well. A self-aligned implantation is performed to form N-type diode diffusion within the light-sensing region. An oblique ion implantation process is then performed to form N-type pocket diffusion directly under the gate electrode. Spacers are formed on sidewalls of the gate electrode. A surface P+ pinning diffusion region is then formed in the diode diffusion region.
    Type: Application
    Filed: October 20, 2005
    Publication date: April 26, 2007
    Inventors: Ching-Wei Chen, Chih-Cheng Hsieh, Chien-Chang Huang
  • Publication number: 20070075219
    Abstract: An active pixel sensor circuit includes a sensor, a reset transistor, a source-follower transistor, and a row-selector transistor. A gate of the row-selector transistor is electrically connected to a drain of the reset transistor. A method for controlling the active pixel sensor circuit includes turning on the row-selector transistor and the reset transistor when resetting the sensor, and turning on the row-selector transistor and the reset transistor when reading a reset signal. In this way, parasitic capacitance at a gate of the source-follower transistor when resetting the sensor is the same as when reading the reset signal.
    Type: Application
    Filed: May 24, 2006
    Publication date: April 5, 2007
    Inventor: Chih-Cheng Hsieh
  • Patent number: 7169633
    Abstract: A method of forming a solid-state image sensor is provided. The method includes the steps of forming a plurality of photosensor elements on a substrate; forming a plurality of color filters on the plurality of photosensors; forming a light blocking member between adjacent color filters; and forming a plurality of microlenses on the plurality of color filters. Each photosensor with each corresponding color filter and microlens is used for receiving an incident light of specific spectrum.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: January 30, 2007
    Assignee: PixArt Imaging Inc.
    Inventors: Chien-Chang Huang, Chih-Cheng Hsieh
  • Publication number: 20060275940
    Abstract: A method for controlling well capacity of a photodiode includes providing a reference voltage, which is greater than a voltage of ground, to a gate of a transfer transistor while exposing the photodiode whose one end is connected to ground, so as to control the well capacity of the photodiode.
    Type: Application
    Filed: April 28, 2006
    Publication date: December 7, 2006
    Inventors: Ming-Chun Su, Chien-Chang Huang, Chih-Cheng Hsieh
  • Publication number: 20060249764
    Abstract: A pinned photodiode sensor with gate-controlled SCR switch includes a pinned photodiode and a gate-controlled SCR switch. The SCR switch includes a P-type substrate, an N? doped region, and an N+ doped region formed on the substrate; a P+ doped region formed on the N? doped region; an oxide layer formed on the P substrate, the N? doped region, the N+ doped region, and the P+ doped region; and a gate formed above the P substrate and the N? doped region. The gate includes a P+ doped region and an N+ doped region. During an exposure procedure, a depletion region will not reach the interface between the oxide layer and the substrate, thereby preventing dark current leakage.
    Type: Application
    Filed: May 4, 2006
    Publication date: November 9, 2006
    Inventors: Chien-Chang Huang, Chih-Cheng Hsieh, Ching-Wei Chen
  • Publication number: 20060017830
    Abstract: An active pixel sensor includes a substrate, a photo-sensing region, a peripheral circuit region, and an isolation region. The photo-sensing region and the peripheral circuit region are formed on the substrate. The isolation region is formed between the photo-sensing region and the peripheral circuit region for isolating the photo-sensing region and the peripheral circuit region. The photo-sensing region induces photo current according to the received light. The peripheral circuit region includes a first transistor having a source connected to a bit line, a second transistor having a gate connected to the photo-sensing region, a source connected to the drain of the first transistor and a drain connected to a voltage source, and a third transistor having a source connected to the photo-sensing region and a drain connected to the voltage source.
    Type: Application
    Filed: November 17, 2004
    Publication date: January 26, 2006
    Inventor: Chih-Cheng Hsieh
  • Publication number: 20050253958
    Abstract: An integrated image fetching device integrates a control circuit and a CMOS sensor on a substrate. The control circuit includes a photometry module used to control a detecting flash, to receive a light signal, and detect the brightness of the light signal. The control circuit also includes a calculating unit used to calculate the magnitude and the period of a flash of a strobe and an exposure parameter, a strobe control module used to control the strobe according to the calculated results of the calculating unit, and an exposure control module used to control an exposure module according to the exposure parameter.
    Type: Application
    Filed: December 9, 2004
    Publication date: November 17, 2005
    Inventor: Chih-Cheng Hsieh
  • Publication number: 20050247854
    Abstract: An auto-focusing device integrates a CMOS sensor and a processing circuit on a substrate. The processing circuit includes an image analyzing circuit used to analyze the imaging signal received from the CMOS sensor, and a focusing controlling circuit used to control focusing.
    Type: Application
    Filed: December 9, 2004
    Publication date: November 10, 2005
    Inventor: Chih-Cheng Hsieh