Abstract: A pulse generation circuit, for outputting a pulse signal at an output terminal, comprises a PMOS, an NMOS and a logic circuit. The PMOS has a source coupled to a first reference voltage level, a drain coupled to the output terminal, and a gate coupled to a first gate control signal. The NMOS has a source coupled to a second reference voltage level, a drain coupled to the output terminal, and a gate coupled to a second gate control signal. The logic circuit generates the first gate control signal according to a control signal and a first logic signal, relating to the second gate control signal and a delay signal of the second gate control signal, and generates the second gate control signal according to the control signal and a second logic signal, relating to the first gate control signal and a delay signal of the first control signal.

Abstract: A method for forming a lithography mask includes forming a capping layer on a reflective multilayer layer, the capping layer comprising a first material, forming a patterned patterning layer on the capping layer, and introducing a secondary material into the capping layer, the secondary material having an atomic number that is smaller than 15.

Abstract: A method for fabricating a pellicle assembly for a lithography process includes fabricating a pellicle frame including a sidewall having a porous material. In some embodiments, the pellicle frame is subjected to an anodization process to form the porous material. The porous material includes a plurality of pore channels extending, in a direction perpendicular to an exterior surface of the sidewall, from the exterior surface to an interior surface of the sidewall. In various embodiments, a pellicle membrane is formed, and the pellicle membrane is attached to the pellicle frame such that the pellicle membrane is suspended by the pellicle frame. Some embodiments disclosed herein further provide a system including a membrane and a pellicle frame that secures the membrane across the pellicle frame. In some examples, a portion of the pellicle frame includes a porous material, where the porous material includes the plurality of pore channels.

Abstract: A pulse generation circuit for outputting a pulse signal at an output terminal, including: a PMOS, an NMOS, and a logic circuit. The PMOS has a source coupled to a first reference voltage level, a drain coupled to the output terminal, and a gate that receives a first gate control signal. The NMOS has a source coupled to a second reference voltage level, a drain coupled to the output terminal, and a gate that receives a second gate control signal. The logic circuit generates the first gate control signal according to a control signal and a first delay signal and generates the second gate control signal according to the control signal and a second delay signal. The first delay signal is relevant to the second gate control signal and the control signal. The second delay signal is relevant to the first gate control signal and the control signal.

Abstract: A method for fabricating a pellicle for EUV lithography processes includes placing a hard mask in contact with a surface of a substrate. In some embodiments, the hard mask is configured to pattern the surface of the substrate to include a first region and a second region surrounding the first region. By way of example, while the mask in positioned in contact with the substrate, an etch process of the substrate is performed to etch the first and second regions into the substrate. Thereafter, an excess substrate region is removed so as to separate the etched first region from the excess substrate region. In various embodiments, the etched and separated first region serves as a pellicle for an extreme ultraviolet (EUV) lithography process.

Abstract: Disclosed is a substrate structure for manufacturing a flexible electronic device, including a supporting layer, a release layer covering the supporting layer with a first area, wherein the release layer is an aromatic polyimide, and a flexible layer covering the supporting layer and the release layer with a second area. The second area is greater than the first area. The adhesion force between the flexible layer and the supporting layer is stronger than the adhesion force between the release layer and the supporting layer.

Abstract: A method for forming a lithography mask includes forming a capping layer on a reflective multilayer layer, the capping layer comprising a first material, forming a patterned patterning layer on the capping layer, and introducing a secondary material into the capping layer, the secondary material having an atomic number that is smaller than 15.

Abstract: An integrated circuit film and a method of manufacturing the same are disclosed. The integrated circuit film includes a circuit board containing a circuit route; a first set of pads located on a first surface of the circuit board and configured to be applicable to ISO 7816 standard; and a semiconductor device mounted on the circuit board for communicating with at least one of the first set of pads. The first set of pads are arranged in two rows and the semiconductor device is mounted on the circuit board in a space between the two rows of pads.

Abstract: An installation card for a smart SIM Overlay and an installation method using the same are provided. The installation card comprises a carrier plate, a first adhesive layer, a smart overlay and a second adhesive layer. The carrier plate has a notch and a surface. The first adhesive layer adheres to the surface of the carrier plate. The smart overlay is adheres to the first adhesive layer, and the smart overlay is positioned corresponding to the notch. The second adhesive layer is adhered to the smart overlay.

Abstract: A pulse generation circuit, for outputting a pulse signal at an output terminal, comprises a PMOS, an NMOS and a logic circuit. The PMOS has a source coupled to a first reference voltage level, a drain coupled to the output terminal, and a gate coupled to a first gate control signal. The NMOS has a source coupled to a second reference voltage level, a drain coupled to the output terminal, and a gate coupled to a second gate control signal. The logic circuit generates the first gate control signal according to a control signal and a first logic signal, relating to the second gate control signal and a delay signal of the second gate control signal, and generates the second gate control signal according to the control signal and a second logic signal, relating to the first gate control signal and a delay signal of the first control signal.

Abstract: A pulse generation circuit for outputting a pulse signal at an output terminal, including: a PMOS, an NMOS, and a logic circuit. The PMOS has a source coupled to a first reference voltage level, a drain coupled to the output terminal, and a gate that receives a first gate control signal. The NMOS has a source coupled to a second reference voltage level, a drain coupled to the output terminal, and a gate that receives a second gate control signal. The logic circuit generates the first gate control signal according to a control signal and a first delay signal and generates the second gate control signal according to the control signal and a second delay signal. The first delay signal is relevant to the second gate control signal and the control signal. The second delay signal is relevant to the first gate control signal and the control signal.

Abstract: An installation card for a smart SIM Overlay and an installation method using the same are provided. The installation card comprises a carrier plate, a first adhesive layer, a smart overlay and a second adhesive layer. The carrier plate has a notch and a surface. The first adhesive layer adheres to the surface of the carrier plate. The smart overlay is adheres to the first adhesive layer, and the smart overlay is positioned corresponding to the notch. The second adhesive layer is adhered to the smart overlay.

Abstract: A signal generating apparatus, for generating a power-on-reset signal, including a bias circuit and a power-on-reset signal generating circuit is disclosed. The bias circuit is for generating an output bias voltage, and includes at least one bipolar junction transistor (BJT), wherein a base terminal of the BJT is coupled to a collector terminal of the BJT, and the output bias voltage is related to an emitter-to-base voltage of the BJT. The power-on-reset signal generating circuit is coupled to the bias circuit, and is for generating a duplicated voltage by duplicating the output bias voltage, wherein the power-on-reset signal is generated according to the duplicated voltage.

Abstract: A vehicle-end database management system is revealed. The vehicle-end database management system includes a read/write controller and a vehicle-end database manager. Data related to vehicles is written into the vehicle-end database manager by the read/write controller. Or data related to vehicles is read from the vehicle-end database manager by the read/write controller. Thus end-users can get the data related to vehicles timely so as to manage vehicles conveniently.

Abstract: Disclosed is a substrate structure for manufacturing a flexible electronic device, including a supporting layer, a release layer covering the supporting layer with a first area, wherein the release layer is an aromatic polyimide, and a flexible layer covering the supporting layer and the release layer with a second area. The second area is greater than the first area. The adhesion force between the flexible layer and the supporting layer is stronger than the adhesion force between the release layer and the supporting layer.

Abstract: A signal generating apparatus, for generating a power-on-reset signal, including a bias circuit and a power-on-reset signal generating circuit is disclosed. The bias circuit is for generating an output bias voltage, and includes at least one bipolar junction transistor (BJT), wherein a base terminal of the BJT is coupled to a collector terminal of the BJT, and the output bias voltage is related to an emitter-to-base voltage of the BJT. The power-on-reset signal generating circuit is coupled to the bias circuit, and is for generating a duplicated voltage by duplicating the output bias voltage, wherein the power-on-reset signal is generated according to the duplicated voltage.

Abstract: A polyimide polymer solution, a polyimide polymer, a transparent film, a display device and a solar cell are provided. The polyimide polymer has at least one of a repeating unit of formula (D) and a repeating unit of formula (J) and at least one of a repeating unit of formula (Q) and a repeating unit of formula (T). One of B and B? is cyclo-aliphatic compound, and the other is aromatic compound, a molar mass ratio of the cyclo-aliphatic compound to the aromatic compound is 1˜4, A and A? are identical or different aromatic diamines, and at least one of A and A? is aromatic diamine with ether groups, and A could be the same as or different from A?.

Abstract: A video playing apparatus includes a connecting port, a video outputting unit, a video processing unit, and a switching unit. The connecting port is coupled to a displaying apparatus, and outputs a first video signal or a second video signal. The video outputting unit generates the first video signal. The video processing unit is coupled to the video outputting unit and the connecting port. The video processing unit receives the first video signal, converting the first video signal to the second video signal, and then outputs the second video signal. The switching unit is coupled to the video outputting unit, the video processing unit, and the connecting port. The switching unit switches the output of the first video signal between the connecting port and the video processing unit according to a control signal.

Abstract: An integrated circuit film and a method of manufacturing the same are disclosed. The integrated circuit film includes a circuit board containing a circuit route; a first set of pads located on a first surface of the circuit board and configured to be applicable to ISO 7816 standard; and a semiconductor device mounted on the circuit board for communicating with at least one of the first set of pads. The first set of pads are arranged in two rows and the semiconductor device is mounted on the circuit board in a space between the two rows of pads.

Abstract: An integrated circuit (IC) film for a smart card is provided. The IC film includes a flexible printed circuit (FPC) board, first electrical contacts, second electrical contacts, and an IC chip. The first electrical contacts are disposed on a first side of the FPC board, and the second electrical contacts are disposed on a second side of the FPC board. The IC chip is disposed on the FPC board and bonded to the leads of the FPC board to thereby form electrical connection. The total thickness of the FPC board and the chip is not larger than 0.5 mm.