Patents by Inventor Chih-Chia Chen
Chih-Chia Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9958895Abstract: Structure and methods for a compensated bandgap reference circuit. A first integrated circuit die having a first bandgap reference circuit with a non-zero temperature coefficient; and having a first output reference signal is provided, a second integrated circuit die having a second bandgap reference circuit with a non-zero temperature coefficient that is of opposite polarity from the temperature coefficient of the first bandgap reference circuit, and having a second output reference signal is provided; an adder circuit disposed on at least one of the first and second integrated circuit dies combines the first and second output reference signals, and outputs a combined reference signal; and connectors for connecting the first and second output signals to the adder circuit are provided. Methods are disclosed for pairing integrated circuit dies with bandgap reference circuits and coupling the dies to form temperature compensated signals.Type: GrantFiled: January 11, 2011Date of Patent: May 1, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Chia Chen, Mark Shane Peng
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Patent number: 9811664Abstract: Unwanted web contents are detected in an endpoint computer. The endpoint computer receives a web page from a website. The reputation of the website is determined and the web page is scanned for malicious codes to protect the endpoint computer from web threats. To further protect the endpoint computer from web threats including mutating unwanted web contents, page structure traits of the web page are generated and compared to page structure traits of other web pages detected to contain unwanted web contents.Type: GrantFiled: August 15, 2011Date of Patent: November 7, 2017Assignee: Trend Micro IncorporatedInventors: Cheng-Hsin Hsu, Peng-Shih Pu, Chih-Chia Chen, Shr-An Su
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Patent number: 9671457Abstract: A method comprises connecting a testing setup having a plurality of probes to a device under test having a plurality of vias, wherein a probe is aligned with a corresponding via of the device under test and conducting a plurality of via electrical characteristic tests through a conductive path comprising the vias, the probes and a plurality of conductive devices, each of which connects two adjacent probes, wherein the conductive devices are in the testing setup.Type: GrantFiled: December 5, 2014Date of Patent: June 6, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Mill-Jer Wang, Chih-Chia Chen, Hung-Chih Lin, Ching-Nen Peng, Hao Chen
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Patent number: 9557354Abstract: A circuit including a first switch receiving an input reference voltage, a second switch receiving an input testing voltage, the first switch and the second switch are electrically connected in parallel. The circuit further includes a first capacitor electrically connected in series with the first switch and the second switch. The circuit further includes a feedback stage comprising a feedback inverter electrically connected in parallel with a feedback switch, where the feedback stage is electrically connected in series with the first capacitor. The circuit further includes a first inverter electrically connected in series to the feedback stage, and a third switch electrically connected in series with the first inverter. The circuit further includes a second inverter electrically connected in parallel to a third inverter, the second inverter and the third inverter are electrically connected in series to the third switch, and the third inverter outputs a first output signal.Type: GrantFiled: January 31, 2012Date of Patent: January 31, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Chia Chen, Kuan-Yu Lin, Chin-Chou Liu
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Publication number: 20150087089Abstract: A method comprises connecting a testing setup having a plurality of probes to a device under test having a plurality of vias, wherein a probe is aligned with a corresponding via of the device under test and conducting a plurality of via electrical characteristic tests through a conductive path comprising the vias, the probes and a plurality of conductive devices, each of which connects two adjacent probes, wherein the conductive devices are in the testing setup.Type: ApplicationFiled: December 5, 2014Publication date: March 26, 2015Inventors: Mill-Jer Wang, Chih-Chia Chen, Hung-Chih Lin, Ching-Nen Peng, Hao Chen
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Patent number: 8922230Abstract: A three dimensional (3D) integrated circuit (IC) testing apparatus includes a plurality of connection devices. When a device under test (DUT) such as an interposer or a 3D IC formed by a plurality of 3D dies operates in a testing mode, the 3D IC testing apparatus is coupled to the DUT via a variety of interface channels such as probes. The connection devices and a variety of through silicon vias (TSVs) in the DUT form a TSV chain so that an electrical characteristic test of the variety of TSVs can be tested all at once.Type: GrantFiled: May 11, 2011Date of Patent: December 30, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Mill-Jer Wang, Chih-Chia Chen, Hung-Chih Lin, Ching-Nen Peng, Hao Chen
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Patent number: 8856710Abstract: A method comprises analyzing front side conductive patterns and back side conductive patterns on a semiconductor interposer using a machine implemented RC extraction tool, and outputting data representing a plurality of respective RC nodes from the RC extraction tool to a tangible persistent machine readable storage medium. A substrate mesh model of the semiconductor interposer is generated, having a plurality of substrate mesh nodes. Each substrate mesh node is connected to adjacent ones of the plurality of substrate mesh nodes by respective substrate impedance elements. A set of inputs to a timing analysis tool is formed. The plurality of RC nodes are connected to ones of the plurality of substrate mesh nodes of the substrate mesh model. The set of inputs is stored in a tangible machine readable storage medium.Type: GrantFiled: June 29, 2011Date of Patent: October 7, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chao-Yang Yeh, Ze-Ming Wu, Meng-Lin Chung, Chih-Chia Chen, Li-Fu Ding, Sa-Lly Liu
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Publication number: 20130193981Abstract: A circuit including a first switch receiving an input reference voltage, a second switch receiving an input testing voltage, the first switch and the second switch are electrically connected in parallel. The circuit further includes a first capacitor electrically connected in series with the first switch and the second switch. The circuit further includes a feedback stage comprising a feedback inverter electrically connected in parallel with a feedback switch, where the feedback stage is electrically connected in series with the first capacitor. The circuit further includes a first inverter electrically connected in series to the feedback stage, and a third switch electrically connected in series with the first inverter. The circuit further includes a second inverter electrically connected in parallel to a third inverter, the second inverter and the third inverter are electrically connected in series to the third switch, and the third inverter outputs a first output signal.Type: ApplicationFiled: January 31, 2012Publication date: August 1, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Chia CHEN, Kuan-Yu LIN, Chin-Chou LIU
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Patent number: 8350603Abstract: A circuit includes an inverter. The inverter inverts an input signal having an input low voltage level and an input high voltage level to form an output signal having an output high voltage level and an output low voltage level. Compared to the input high voltage level, the output high voltage level is lowered. Alternatively or additionally, compared to the input low voltage level, the output low voltage level is raised.Type: GrantFiled: January 12, 2011Date of Patent: January 8, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Chih-Chia Chen
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Publication number: 20130007692Abstract: A method comprises analyzing front side conductive patterns and back side conductive patterns on a semiconductor interposer using a machine implemented RC extraction tool, and outputting data representing a plurality of respective RC nodes from the RC extraction tool to a tangible persistent machine readable storage medium. A substrate mesh model of the semiconductor interposer is generated, having a plurality of substrate mesh nodes. Each substrate mesh node is connected to adjacent ones of the plurality of substrate mesh nodes by respective substrate impedance elements. A set of inputs to a timing analysis tool is formed. The plurality of RC nodes are connected to ones of the plurality of substrate mesh nodes of the substrate mesh model. The set of inputs is stored in a tangible machine readable storage medium.Type: ApplicationFiled: June 29, 2011Publication date: January 3, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chao-Yang Yeh, Ze-Ming Wu, Meng-Lin Chung, Chih-Chia Chen, Li-Fu Ding, Sa-Lly Liu
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Patent number: 8316440Abstract: Detection for pharming attacks and specifically for changes in name-to-IP resolutions on a computer system using rules is described. The DNS settings and the Hosts file on a computer system are monitored and their modification information is saved as a part of the historical data over time. When an IP address is determined for a host name, various rules are applied to the IP address in connection with the saved historical data, such that each rule produces a score based on various criteria. Different rules may have different weights assigned to their scores. The scores of all the rules are summed up to produce a final score. If the final score is above a predefined value, then there is a suspicious change in the IP address, and an alert is sent. Otherwise, the host name and the IP address are saved as a part of the historical data.Type: GrantFiled: October 30, 2007Date of Patent: November 20, 2012Assignee: Trend Micro, Inc.Inventors: Sheng-Chi Hsieh, Chao-Yu Chen, Chih-Chia Chen
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Publication number: 20120286814Abstract: A three dimensional (3D) integrated circuit (IC) testing apparatus comprises a plurality of connection devices. When a device under test (DUT) such as an interposer or a 3D IC formed by a plurality of 3D dies operates in a testing mode, the 3D IC testing apparatus is coupled to the DUT via a variety of interface channels such as probes. The connection devices and a variety of through silicon vias (TSVs) in the DUT form a TSV chain so that a electrical characteristic test of the variety of TSVs can be tested all at once.Type: ApplicationFiled: May 11, 2011Publication date: November 15, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Mill-Jer Wang, Chih-Chia Chen, Hung-Chih Lin, Ching-Nen Peng, Hao Chen
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Patent number: 8269350Abstract: An interconnection component includes a plurality of through-substrate vias (TSVs) penetrating through a substrate. The plurality of TSVs includes an active TSV having a first end and a second end. The first end of the active TSV is electrically coupled to a signal-providing circuit. The second end of the active TSV is electrically coupled to an additional package component bonded to the interconnection component. The plurality of TSVs further includes a dummy TSV having a first end and a second end, wherein the first end is electrically coupled to the signal-providing circuit, and wherein the second end is open ended.Type: GrantFiled: May 31, 2011Date of Patent: September 18, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Chia Chen, Chao-Yang Yeh, Meng-Lin Chung
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Publication number: 20120176186Abstract: Structure and methods for a compensated bandgap reference circuit. A first integrated circuit die having a first bandgap reference circuit with a non-zero temperature coefficient; and having a first output reference signal is provided, a second integrated circuit die having a second bandgap reference circuit with a non-zero temperature coefficient that is of opposite polarity from the temperature coefficient of the first bandgap reference circuit, and having a second output reference signal is provided; an adder circuit disposed on at least one of the first and second integrated circuit dies combines the first and second output reference signals, and outputs a combined reference signal; and connectors for connecting the first and second output signals to the adder circuit are provided. Methods are disclosed for pairing integrated circuit dies with bandgap reference circuits and coupling the dies to form temperature compensated signals.Type: ApplicationFiled: January 11, 2011Publication date: July 12, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Chia Chen, Mark Shane Peng
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Publication number: 20120176189Abstract: A circuit includes an inverter. The inverter inverts an input signal having an input low voltage level and an input high voltage level to form an output signal having an output high voltage level and an output low voltage level. Compared to the input high voltage level, the output high voltage level is lowered. Alternatively or additionally, compared to the input low voltage level, the output low voltage level is raised.Type: ApplicationFiled: January 12, 2011Publication date: July 12, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: Chih-Chia CHEN
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Patent number: 8193082Abstract: A circuit signal connection interface, a manufacturing method thereof, and an electronic device using the same are provided. The circuit signal connection interface includes a first signal line and a second signal line juxtaposed to each other, an insulation layer, and a first conductive pad. The first conductive pad electrically connects to the first signal line, and crosses the second signal line. Te insulation layer is disposed between the second signal line and the first conductive pad. The electronic device further includes a circuit device including a first conducting bump and a second conducting bump connected to each other in a parallel manner. The first conducting bump electrically connects to a first portion of the first conductive pad while the second conducting bump electrically connects to a second portion of the first conductive pad.Type: GrantFiled: March 15, 2011Date of Patent: June 5, 2012Assignee: AU Optronics CorporationInventor: Chih-Chia Chen
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Patent number: 8007161Abstract: A backlight module is provided. The backlight module includes a backplate, at least one supporter, and a plurality of light emitting devices. The supporter is disposed on the backplate, and includes a supporting portion and a buffering portion. The supporting portion is disposed between the buffering portion and the backplate. The elastic coefficient of the buffering portion is smaller than the elastic coefficient of the supporting portion. The light emitting devices are also disposed on the backplate. The supporter is disposed between the light emitting devices. The buffering portion of the supporter of the backlight module is adapted for buffering an external force applied upon the supporting porter or the element disposed thereupon.Type: GrantFiled: December 29, 2008Date of Patent: August 30, 2011Assignee: Au Optronics CorporationInventors: Fu-Tung Chen, Shih-Che Fu, Chih-Chia Chen, Chung-Te Lee
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Publication number: 20110165773Abstract: A circuit signal connection interface, a manufacturing method thereof, and an electronic device using the same are provided. The circuit signal connection interface includes a first signal line and a second signal line juxtaposed to each other, an insulation layer, and a first conductive pad. The first conductive pad electrically connects to the first signal line, and crosses the second signal line. The insulation layer is disposed between the second signal line and the first conductive pad. The electronic device further includes a circuit device including a first conducting bump and a second conducting bump connected to each other in a parallel manner. The first conducting bump electrically connects to a first portion of the first conductive pad while the second conducting bump electrically connects to a second portion of the first conductive pad.Type: ApplicationFiled: March 15, 2011Publication date: July 7, 2011Applicant: AU OPTRONICS CORPORATIONInventor: Chih-Chia Chen
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Patent number: 7928588Abstract: A circuit signal connection interface, a manufacturing method thereof, and an electronic device using the same are provided. The circuit signal connection interface includes a first signal line and a second signal line juxtaposed to each other, an insulation layer, and a first conductive pad. The first conductive pad electrically connects to the first signal line, and crosses the second signal line. The insulation layer is disposed between the second signal line and the first conductive pad. The electronic device further includes a circuit device including a first conducting bump and a second conducting bump connected to each other in a parallel manner. The first conducting bump electrically connects to a first portion of the first conductive pad while the second conducting bump electrically connects to a second portion of the first conductive pad.Type: GrantFiled: May 29, 2008Date of Patent: April 19, 2011Assignee: Au Optronics CorporationInventor: Chih-Chia Chen
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Patent number: 7920222Abstract: A liquid crystal display (LCD) includes a backlight module, a cell module installed in front of the backlight module, and a front frame which includes a frame body with holes and buffer material. The buffer material has a first part disposed in the holes and fixed to the cell module and backlight module through the front frame, and a second part sandwiched between the frame body and cell module. A method for manufacturing a LCD device is also provided, including forming a buffer material on a frame body by injection molding, firmly connecting the frame body, a cell module, and a backlight module, and locating the buffer material between the frame body and cell module.Type: GrantFiled: March 7, 2008Date of Patent: April 5, 2011Assignee: Au Optronics Corp.Inventors: Chih-Chia Chen, Chien-Yuan Chen