Patents by Inventor Chih-Chiang Hsieh

Chih-Chiang Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240389240
    Abstract: An embodiment composite material for semiconductor package mount applications may include a first component including a tin-silver-copper alloy and a second component including a tin-bismuth alloy or a tin-indium alloy. The composite material may form a reflowed bonding material having a room temperature tensile strength in a range from 80 MPa to 100 MPa when subjected to a reflow process. The reflowed bonding material may include a weight fraction of bismuth that is in a range from approximately 4% to approximately 15%. The reflowed bonding material may an alloy that is solid solution strengthened by a presence of bismuth or indium that is dissolved within the reflowed bonding material or a solid solution phase that includes a minor component of bismuth dissolved within a major component of tin. In some embodiments, the reflowed bonding material may include intermetallic compounds formed as precipitates such as Ag3Sn and/or Cu6Sn5.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Inventors: Chao-Wei Chiu, Chih-Chiang Tsao, Jen-Jui Yu, Hsuan-Ting Kuo, Hsiu-Jen Lin, Ching-Hua Hsieh
  • Publication number: 20240387346
    Abstract: Embodiments include a device. The device includes an interposer, a package substrate, and conductive connectors bonding the package substrate to the interposer. Each of the conductive connectors have convex sidewalls. A first subset of the conductive connectors are disposed in a center of the package substrate in a top-down view. A second subset of the conductive connectors are disposed in an edge/corner of the package substrate in the top-down view. Each of the second subset of the conductive connectors have a greater height than each of the first subset of the conductive connectors.
    Type: Application
    Filed: August 7, 2023
    Publication date: November 21, 2024
    Inventors: Chih-Chiang Tsao, Chao-Wei Chiu, Hsin Liang Chen, Chia-Shen Cheng, Hsiu-Jen Lin, Ching-Hua Hsieh
  • Publication number: 20240370624
    Abstract: An electronic design flow generates an electronic architectural design layout for analog circuitry from a schematic diagram. The electronic design flow assigns analog circuits of the schematic diagram to various categories of analog circuits. The electronic design flow places various analog standard cells corresponding to these categories of analog circuits into analog placement sites assigned to the analog circuits. These analog standard cells have a uniform cell height which allows these analog standard cells to be readily connected or merged to digital standard cells which decreases the area of the electronic architectural design layout. This uniformity in height between these analog standard cells additionally provides a more reliable yield when compared to non-uniform analog standard cells.
    Type: Application
    Filed: July 15, 2024
    Publication date: November 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ting LU, Chih-Chiang Chang, Chung-Peng Hsieh, Chung-Chieh Yang, Yung-Chow Peng, Yung-Shun Chen, Tai-Yi Chen, Nai Chen Cheng
  • Publication number: 20240369627
    Abstract: A device for measuring a frequency response of a wafer is provided. The device includes a first oscillator, a clock generator, a first circuit, and a first driver. The first oscillator configured to provide a first signal having a first frequency. The clock generator is configured to receive the first signal and generate a first clock signal and a second clock signal having the first frequency. The first circuit on the wafer and having a first number of parallelly connected ring oscillators. The first driver is coupled to the first circuit and the clock generator, and configured to receive the first clock signal and the second clock signal, and drive the first circuit. A first portion of each ring oscillator of the first circuit is electrically disconnected from a second portion of each ring oscillator of the first circuit.
    Type: Application
    Filed: July 17, 2024
    Publication date: November 7, 2024
    Inventors: YUNG-SHUN CHEN, CHIH-CHIANG CHANG, CHUNG-PENG HSIEH, YUNG-CHOW PENG
  • Publication number: 20240371813
    Abstract: A semiconductor package includes a substrate, a semiconductor device over the substrate and a plurality of solder joint structures bonded between the semiconductor device and the substrate, wherein each of the plurality of solder joint structures includes, by weight percent, 2% to 23% of Indium (In).
    Type: Application
    Filed: July 15, 2024
    Publication date: November 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jen-Jui Yu, Chih-Chiang Tsao, Hsuan-Ting Kuo, Mao-Yen Chang, Hsiu-Jen Lin, Ching-Hua Hsieh, Hao-Jan Pei
  • Patent number: 12117489
    Abstract: A device for measuring characteristics of a wafer is provided. The device includes a first circuit on the wafer and having a first number of parallelly connected oscillators, and a second circuit on the wafer and having the first number of parallelly connected oscillators; wherein a first portion of the second circuit is disconnected from a second portion of the second circuit.
    Type: Grant
    Filed: September 12, 2020
    Date of Patent: October 15, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yung-Shun Chen, Chih-Chiang Chang, Chung-Peng Hsieh, Yung-Chow Peng
  • Publication number: 20240332215
    Abstract: A package structure and a method of forming the same are provided. The package structure includes a die, an encapsulant, a redistribution layer (RDL) structure, a passive device, and a plurality of dummy items. The encapsulant laterally encapsulates the die. The RDL structure is disposed on the die and the encapsulant. The passive device is disposed on and electrically bonded to the RDL structure. The plurality of dummy items are disposed on the RDL structure and laterally aside the passive device, wherein top surfaces of the plurality of dummy items are higher than a top surface of the passive device.
    Type: Application
    Filed: June 12, 2024
    Publication date: October 3, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jen-Jui Yu, Ching-Hua Hsieh, Cheng-Ting Chen, Hsiu-Jen Lin, Wei-Yu Chen, Chih-Chiang Tsao, Chao-Wei Chiu
  • Publication number: 20240329517
    Abstract: A pellicle includes a frame having an attachment surface configured to attach to a photomask, wherein the frame comprises a vent hole. The pellicle further includes a filter covering the vent hole, wherein the filter directly contacts an inner surface of the frame, and the filter extends in a direction parallel to the attachment surface. The pellicle further includes a membrane extending over a top surface of the frame.
    Type: Application
    Filed: June 14, 2024
    Publication date: October 3, 2024
    Inventors: Chue San YOO, Chih-Chiang TU, Chien-Cheng CHEN, Jong-Yuh CHANG, Kun-Lung HSIEH, Pei-Cheng HSU, Hsin-Chang LEE, Yun-Yue LIN
  • Patent number: 12107064
    Abstract: A semiconductor package includes a substrate, a semiconductor device over the substrate and a plurality of solder joint structures bonded between the semiconductor device and the substrate, wherein each of the plurality of solder joint structures includes, by weight percent, 2% to 23% of Indium (In).
    Type: Grant
    Filed: April 13, 2022
    Date of Patent: October 1, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jen-Jui Yu, Chih-Chiang Tsao, Hsuan-Ting Kuo, Mao-Yen Chang, Hsiu-Jen Lin, Ching-Hua Hsieh, Hao-Jan Pei
  • Publication number: 20240312941
    Abstract: An electronic apparatus including a package substrate and a structure disposed on and electrically connected to the package substrate through conductive bumps is provided. The material of the conductive bumps includes a bismuth (Bi) containing alloy or an indium (In) containing alloy. In some embodiments, the bismuth (Bi) containing alloy includes Sn—Ag—Cu—Bi alloy. In some embodiments, a concentration of bismuth (Bi) contained in the Sn—Ag—Cu—Bi alloy ranges from about 1 wt % to about 10 wt %. Methods for forming the Sn—Ag—Cu—Bi alloy are also provided.
    Type: Application
    Filed: March 13, 2023
    Publication date: September 19, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Wei Chiu, Wei-Yu Chen, Chih-Chiang Tsao, Hao-Jan Pei, Hsiu-Jen Lin, Ching-Hua Hsieh
  • Patent number: 12073167
    Abstract: An electronic design flow generates an electronic architectural design layout for analog circuitry from a schematic diagram. The electronic design flow assigns analog circuits of the schematic diagram to various categories of analog circuits. The electronic design flow places various analog standard cells corresponding to these categories of analog circuits into analog placement sites assigned to the analog circuits. These analog standard cells have a uniform cell height which allows these analog standard cells to be readily connected or merged to digital standard cells which decreases the area of the electronic architectural design layout. This uniformity in height between these analog standard cells additionally provides a more reliable yield when compared to non-uniform analog standard cells.
    Type: Grant
    Filed: February 3, 2023
    Date of Patent: August 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Ting Lu, Chih-Chiang Chang, Chung-Peng Hsieh, Chung-Chieh Yang, Yung-Chow Peng, Yung-Shun Chen, Tai-Yi Chen, Nai Chen Cheng
  • Publication number: 20240274589
    Abstract: A manufacturing method of a package-on-package structure includes placing a lower package on a tape, where conductive bumps of the lower package are in contact with the tape; and bonding an upper package to the lower package, where during the bonding, the conductive bumps are pressed against the tape so that a curvature of the respective conductive bump changes.
    Type: Application
    Filed: April 22, 2024
    Publication date: August 15, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsuan-Ting Kuo, Ching-Hua Hsieh, Cheng-Ting Chen, Hsiu-Jen Lin, Hao-Jan Pei, Yu-Peng Tsai, Chia-Lun Chang, Chih-Chiang Tsao, Philip Yu-shuan Chung
  • Patent number: 12051655
    Abstract: A package structure and a method of forming the same are provided. The package structure includes a die, an encapsulant, a redistribution layer (RDL) structure, a passive device, and a plurality of dummy items. The encapsulant laterally encapsulates the die. The RDL structure is disposed on the die and the encapsulant. The passive device is disposed on and electrically bonded to the RDL structure. The plurality of dummy items are disposed on the RDL structure and laterally aside the passive device, wherein top surfaces of the plurality of dummy items are higher than a top surface of the passive device.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: July 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jen-Jui Yu, Ching-Hua Hsieh, Cheng-Ting Chen, Hsiu-Jen Lin, Wei-Yu Chen, Chih-Chiang Tsao, Chao-Wei Chiu
  • Patent number: 12051639
    Abstract: A package structure includes a first package, a second package, a conductive spacer, and a flux portion. The first package includes a semiconductor die. The second package is stacked to the first package. The conductive spacer is disposed between and electrically couples the first package and the second package. The flux portion is disposed between and electrically couples the first package and the conductive spacer, where the flux portion includes a first portion and a second portion separating from the first portion by a gap, and the first portion and the second portion are symmetric about an extending direction of the gap. The gap is overlapped with the conductive spacer.
    Type: Grant
    Filed: March 2, 2022
    Date of Patent: July 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chiang Tsao, Chao-Wei Chiu, Jen-Jui Yu, Hsiu-Jen Lin, Ching-Hua Hsieh
  • Patent number: 10928383
    Abstract: A method for predicting an effect of a medication or a treatment regimen to a subject suffering from a cancer, the method comprises: (A) obtaining a tissue from the subject; (B) dissociating the tissue to obtain a multicellular cluster, wherein the multicellular cluster comprises the cancer cell; (C) culturing the multicellular cluster on a cellulose sponge; (D) exposing the cultured multicellular cluster to the medication or the treatment regimen; and (E) measuring a first survival rate of the cancer cell before exposing to the medication or the treatment regimen and a second survival rate of the cancer cell after exposing to the medication or the treatment regimen, when the second survival rate is lower than the first survival rate, the method predicts positive effect of the medication or the treatment regimen to the subject.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: February 23, 2021
    Assignee: SHANXI PISHON BIOMEDICAL TECHNOLOGY CO., LTD
    Inventors: Chih-Chiang Hsieh, Yen Chang
  • Publication number: 20180348204
    Abstract: A method for predicting an effect of a medication or a treatment regimen to a subject suffering from a cancer, the method comprises: (A) obtaining a tissue from the subject; (B) dissociating the tissue to obtain a multicellular cluster, wherein the multicellular cluster comprises the cancer cell; (C) culturing the multicellular cluster on a cellulose sponge; (D) exposing the cultured multicellular cluster to the medication or the treatment regimen; and (E) measuring a first survival rate of the cancer cell before exposing to the medication or the treatment regimen and a second survival rate of the cancer cell after exposing to the medication or the treatment regimen, when the second survival rate is lower than the first survival rate, the method predicts positive effect of the medication or the treatment regimen to the subject.
    Type: Application
    Filed: May 31, 2018
    Publication date: December 6, 2018
    Applicant: PISHON Biomedical Co., Ltd.
    Inventors: Chih-Chiang Hsieh, Yen Chang
  • Patent number: 9839658
    Abstract: The present invention relates to a method for treating retinal ischemia, or a disease, condition, or disorder associated with retinal ischemia, in a subject in need thereof, comprising administering to said subject a therapeutically effective amount of a composition comprising Chi-Ju-Di-Huang-Wan, wherein the Chi-Ju-Di-Huang-Wan consists of Rehmanniae Radix Preparata, Corni Fructus, Rhizoma Dioscoreae, Poria, Cortex Moutan Radicis, Alismatis Rhizome, Fructus Lycii, and Chrysanthemi Flos.
    Type: Grant
    Filed: November 27, 2015
    Date of Patent: December 12, 2017
    Inventors: Hsiao-Ming Chao, Chih-Chiang Hsieh
  • Publication number: 20170151295
    Abstract: The present invention relates to a method for treating retinal ischemia, or a disease, condition, or disorder associated with retinal ischemia, in a subject in need thereof, comprising administering to said subject a therapeutically effective amount of a composition comprising Chi-Ju-Di-Huang-Wan, wherein the Chi-Ju-Di-Huang-Wan consists of Rehmanniae Radix Preparata, Corni Fructus, Rhizoma Diocoreae, Poria, Cortex Moutan Redicis, Alismatis Rhizome, Fructus Lycii, and Chrysanthemi Flos.
    Type: Application
    Filed: November 27, 2015
    Publication date: June 1, 2017
    Inventors: Hsiao-Ming Chao, Chih-Chiang Hsieh
  • Patent number: 9225693
    Abstract: A major management apparatus, an authorized management apparatus, an electronic apparatus for delegation management, and delegation management methods thereof are provided. The major management apparatus generates a first and a second delegation deployment messages and respectively transmits them to the authorized management apparatus and the electronic apparatus. The authorized management apparatus encrypts an original authorized operation message into an authorized operation message by an authorization key included in the first delegation deployment message and transmits the authorized operation message to the electronic apparatus. The original authorized operation message includes an operation task message and a right level. The electronic apparatus decrypts the authorized operation message into the original authorized operation message by the authorization key included in the second delegation deployment message and performs an operation according to the operation task message and the right level.
    Type: Grant
    Filed: January 26, 2015
    Date of Patent: December 29, 2015
    Assignee: Institute For Information Industry
    Inventors: Jui-Ming Wu, You-Lian Huang, Chih-Chiang Hsieh, Emery Jou
  • Patent number: 9210136
    Abstract: A major management apparatus, an authorized management apparatus, an electronic apparatus for delegation management, and delegation management methods thereof are provided. The major management apparatus generates a first and a second delegation deployment messages and respectively transmits them to the authorized management apparatus and the electronic apparatus. The authorized management apparatus encrypts an original authorized operation message into an authorized operation message by an authorization key included in the first delegation deployment message and transmits the authorized operation message to the electronic apparatus. The original authorized operation message includes an operation task message and a right level. The electronic apparatus decrypts the authorized operation message into the original authorized operation message by the authorization key included in the second delegation deployment message and performs an operation according to the operation task message and the right level.
    Type: Grant
    Filed: January 26, 2015
    Date of Patent: December 8, 2015
    Assignee: Institute For Information Industry
    Inventors: Jui-Ming Wu, You-Lian Huang, Chih-Chiang Hsieh, Emery Jou