Patents by Inventor Chih-Chiang Hsieh
Chih-Chiang Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240371813Abstract: A semiconductor package includes a substrate, a semiconductor device over the substrate and a plurality of solder joint structures bonded between the semiconductor device and the substrate, wherein each of the plurality of solder joint structures includes, by weight percent, 2% to 23% of Indium (In).Type: ApplicationFiled: July 15, 2024Publication date: November 7, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jen-Jui Yu, Chih-Chiang Tsao, Hsuan-Ting Kuo, Mao-Yen Chang, Hsiu-Jen Lin, Ching-Hua Hsieh, Hao-Jan Pei
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Publication number: 20240370624Abstract: An electronic design flow generates an electronic architectural design layout for analog circuitry from a schematic diagram. The electronic design flow assigns analog circuits of the schematic diagram to various categories of analog circuits. The electronic design flow places various analog standard cells corresponding to these categories of analog circuits into analog placement sites assigned to the analog circuits. These analog standard cells have a uniform cell height which allows these analog standard cells to be readily connected or merged to digital standard cells which decreases the area of the electronic architectural design layout. This uniformity in height between these analog standard cells additionally provides a more reliable yield when compared to non-uniform analog standard cells.Type: ApplicationFiled: July 15, 2024Publication date: November 7, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Ting LU, Chih-Chiang Chang, Chung-Peng Hsieh, Chung-Chieh Yang, Yung-Chow Peng, Yung-Shun Chen, Tai-Yi Chen, Nai Chen Cheng
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Publication number: 20240369627Abstract: A device for measuring a frequency response of a wafer is provided. The device includes a first oscillator, a clock generator, a first circuit, and a first driver. The first oscillator configured to provide a first signal having a first frequency. The clock generator is configured to receive the first signal and generate a first clock signal and a second clock signal having the first frequency. The first circuit on the wafer and having a first number of parallelly connected ring oscillators. The first driver is coupled to the first circuit and the clock generator, and configured to receive the first clock signal and the second clock signal, and drive the first circuit. A first portion of each ring oscillator of the first circuit is electrically disconnected from a second portion of each ring oscillator of the first circuit.Type: ApplicationFiled: July 17, 2024Publication date: November 7, 2024Inventors: YUNG-SHUN CHEN, CHIH-CHIANG CHANG, CHUNG-PENG HSIEH, YUNG-CHOW PENG
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Patent number: 12117489Abstract: A device for measuring characteristics of a wafer is provided. The device includes a first circuit on the wafer and having a first number of parallelly connected oscillators, and a second circuit on the wafer and having the first number of parallelly connected oscillators; wherein a first portion of the second circuit is disconnected from a second portion of the second circuit.Type: GrantFiled: September 12, 2020Date of Patent: October 15, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yung-Shun Chen, Chih-Chiang Chang, Chung-Peng Hsieh, Yung-Chow Peng
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Publication number: 20240329517Abstract: A pellicle includes a frame having an attachment surface configured to attach to a photomask, wherein the frame comprises a vent hole. The pellicle further includes a filter covering the vent hole, wherein the filter directly contacts an inner surface of the frame, and the filter extends in a direction parallel to the attachment surface. The pellicle further includes a membrane extending over a top surface of the frame.Type: ApplicationFiled: June 14, 2024Publication date: October 3, 2024Inventors: Chue San YOO, Chih-Chiang TU, Chien-Cheng CHEN, Jong-Yuh CHANG, Kun-Lung HSIEH, Pei-Cheng HSU, Hsin-Chang LEE, Yun-Yue LIN
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Publication number: 20240332215Abstract: A package structure and a method of forming the same are provided. The package structure includes a die, an encapsulant, a redistribution layer (RDL) structure, a passive device, and a plurality of dummy items. The encapsulant laterally encapsulates the die. The RDL structure is disposed on the die and the encapsulant. The passive device is disposed on and electrically bonded to the RDL structure. The plurality of dummy items are disposed on the RDL structure and laterally aside the passive device, wherein top surfaces of the plurality of dummy items are higher than a top surface of the passive device.Type: ApplicationFiled: June 12, 2024Publication date: October 3, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jen-Jui Yu, Ching-Hua Hsieh, Cheng-Ting Chen, Hsiu-Jen Lin, Wei-Yu Chen, Chih-Chiang Tsao, Chao-Wei Chiu
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Patent number: 12107064Abstract: A semiconductor package includes a substrate, a semiconductor device over the substrate and a plurality of solder joint structures bonded between the semiconductor device and the substrate, wherein each of the plurality of solder joint structures includes, by weight percent, 2% to 23% of Indium (In).Type: GrantFiled: April 13, 2022Date of Patent: October 1, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jen-Jui Yu, Chih-Chiang Tsao, Hsuan-Ting Kuo, Mao-Yen Chang, Hsiu-Jen Lin, Ching-Hua Hsieh, Hao-Jan Pei
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Publication number: 20240312941Abstract: An electronic apparatus including a package substrate and a structure disposed on and electrically connected to the package substrate through conductive bumps is provided. The material of the conductive bumps includes a bismuth (Bi) containing alloy or an indium (In) containing alloy. In some embodiments, the bismuth (Bi) containing alloy includes Sn—Ag—Cu—Bi alloy. In some embodiments, a concentration of bismuth (Bi) contained in the Sn—Ag—Cu—Bi alloy ranges from about 1 wt % to about 10 wt %. Methods for forming the Sn—Ag—Cu—Bi alloy are also provided.Type: ApplicationFiled: March 13, 2023Publication date: September 19, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chao-Wei Chiu, Wei-Yu Chen, Chih-Chiang Tsao, Hao-Jan Pei, Hsiu-Jen Lin, Ching-Hua Hsieh
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Patent number: 12073167Abstract: An electronic design flow generates an electronic architectural design layout for analog circuitry from a schematic diagram. The electronic design flow assigns analog circuits of the schematic diagram to various categories of analog circuits. The electronic design flow places various analog standard cells corresponding to these categories of analog circuits into analog placement sites assigned to the analog circuits. These analog standard cells have a uniform cell height which allows these analog standard cells to be readily connected or merged to digital standard cells which decreases the area of the electronic architectural design layout. This uniformity in height between these analog standard cells additionally provides a more reliable yield when compared to non-uniform analog standard cells.Type: GrantFiled: February 3, 2023Date of Patent: August 27, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung-Ting Lu, Chih-Chiang Chang, Chung-Peng Hsieh, Chung-Chieh Yang, Yung-Chow Peng, Yung-Shun Chen, Tai-Yi Chen, Nai Chen Cheng
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Publication number: 20240274589Abstract: A manufacturing method of a package-on-package structure includes placing a lower package on a tape, where conductive bumps of the lower package are in contact with the tape; and bonding an upper package to the lower package, where during the bonding, the conductive bumps are pressed against the tape so that a curvature of the respective conductive bump changes.Type: ApplicationFiled: April 22, 2024Publication date: August 15, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsuan-Ting Kuo, Ching-Hua Hsieh, Cheng-Ting Chen, Hsiu-Jen Lin, Hao-Jan Pei, Yu-Peng Tsai, Chia-Lun Chang, Chih-Chiang Tsao, Philip Yu-shuan Chung
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Patent number: 12051655Abstract: A package structure and a method of forming the same are provided. The package structure includes a die, an encapsulant, a redistribution layer (RDL) structure, a passive device, and a plurality of dummy items. The encapsulant laterally encapsulates the die. The RDL structure is disposed on the die and the encapsulant. The passive device is disposed on and electrically bonded to the RDL structure. The plurality of dummy items are disposed on the RDL structure and laterally aside the passive device, wherein top surfaces of the plurality of dummy items are higher than a top surface of the passive device.Type: GrantFiled: July 16, 2021Date of Patent: July 30, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jen-Jui Yu, Ching-Hua Hsieh, Cheng-Ting Chen, Hsiu-Jen Lin, Wei-Yu Chen, Chih-Chiang Tsao, Chao-Wei Chiu
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Patent number: 12051639Abstract: A package structure includes a first package, a second package, a conductive spacer, and a flux portion. The first package includes a semiconductor die. The second package is stacked to the first package. The conductive spacer is disposed between and electrically couples the first package and the second package. The flux portion is disposed between and electrically couples the first package and the conductive spacer, where the flux portion includes a first portion and a second portion separating from the first portion by a gap, and the first portion and the second portion are symmetric about an extending direction of the gap. The gap is overlapped with the conductive spacer.Type: GrantFiled: March 2, 2022Date of Patent: July 30, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Chiang Tsao, Chao-Wei Chiu, Jen-Jui Yu, Hsiu-Jen Lin, Ching-Hua Hsieh
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Patent number: 10928383Abstract: A method for predicting an effect of a medication or a treatment regimen to a subject suffering from a cancer, the method comprises: (A) obtaining a tissue from the subject; (B) dissociating the tissue to obtain a multicellular cluster, wherein the multicellular cluster comprises the cancer cell; (C) culturing the multicellular cluster on a cellulose sponge; (D) exposing the cultured multicellular cluster to the medication or the treatment regimen; and (E) measuring a first survival rate of the cancer cell before exposing to the medication or the treatment regimen and a second survival rate of the cancer cell after exposing to the medication or the treatment regimen, when the second survival rate is lower than the first survival rate, the method predicts positive effect of the medication or the treatment regimen to the subject.Type: GrantFiled: May 31, 2018Date of Patent: February 23, 2021Assignee: SHANXI PISHON BIOMEDICAL TECHNOLOGY CO., LTDInventors: Chih-Chiang Hsieh, Yen Chang
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Publication number: 20180348204Abstract: A method for predicting an effect of a medication or a treatment regimen to a subject suffering from a cancer, the method comprises: (A) obtaining a tissue from the subject; (B) dissociating the tissue to obtain a multicellular cluster, wherein the multicellular cluster comprises the cancer cell; (C) culturing the multicellular cluster on a cellulose sponge; (D) exposing the cultured multicellular cluster to the medication or the treatment regimen; and (E) measuring a first survival rate of the cancer cell before exposing to the medication or the treatment regimen and a second survival rate of the cancer cell after exposing to the medication or the treatment regimen, when the second survival rate is lower than the first survival rate, the method predicts positive effect of the medication or the treatment regimen to the subject.Type: ApplicationFiled: May 31, 2018Publication date: December 6, 2018Applicant: PISHON Biomedical Co., Ltd.Inventors: Chih-Chiang Hsieh, Yen Chang
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Patent number: 9839658Abstract: The present invention relates to a method for treating retinal ischemia, or a disease, condition, or disorder associated with retinal ischemia, in a subject in need thereof, comprising administering to said subject a therapeutically effective amount of a composition comprising Chi-Ju-Di-Huang-Wan, wherein the Chi-Ju-Di-Huang-Wan consists of Rehmanniae Radix Preparata, Corni Fructus, Rhizoma Dioscoreae, Poria, Cortex Moutan Radicis, Alismatis Rhizome, Fructus Lycii, and Chrysanthemi Flos.Type: GrantFiled: November 27, 2015Date of Patent: December 12, 2017Inventors: Hsiao-Ming Chao, Chih-Chiang Hsieh
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Publication number: 20170151295Abstract: The present invention relates to a method for treating retinal ischemia, or a disease, condition, or disorder associated with retinal ischemia, in a subject in need thereof, comprising administering to said subject a therapeutically effective amount of a composition comprising Chi-Ju-Di-Huang-Wan, wherein the Chi-Ju-Di-Huang-Wan consists of Rehmanniae Radix Preparata, Corni Fructus, Rhizoma Diocoreae, Poria, Cortex Moutan Redicis, Alismatis Rhizome, Fructus Lycii, and Chrysanthemi Flos.Type: ApplicationFiled: November 27, 2015Publication date: June 1, 2017Inventors: Hsiao-Ming Chao, Chih-Chiang Hsieh
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Patent number: 9225693Abstract: A major management apparatus, an authorized management apparatus, an electronic apparatus for delegation management, and delegation management methods thereof are provided. The major management apparatus generates a first and a second delegation deployment messages and respectively transmits them to the authorized management apparatus and the electronic apparatus. The authorized management apparatus encrypts an original authorized operation message into an authorized operation message by an authorization key included in the first delegation deployment message and transmits the authorized operation message to the electronic apparatus. The original authorized operation message includes an operation task message and a right level. The electronic apparatus decrypts the authorized operation message into the original authorized operation message by the authorization key included in the second delegation deployment message and performs an operation according to the operation task message and the right level.Type: GrantFiled: January 26, 2015Date of Patent: December 29, 2015Assignee: Institute For Information IndustryInventors: Jui-Ming Wu, You-Lian Huang, Chih-Chiang Hsieh, Emery Jou
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Patent number: 9210136Abstract: A major management apparatus, an authorized management apparatus, an electronic apparatus for delegation management, and delegation management methods thereof are provided. The major management apparatus generates a first and a second delegation deployment messages and respectively transmits them to the authorized management apparatus and the electronic apparatus. The authorized management apparatus encrypts an original authorized operation message into an authorized operation message by an authorization key included in the first delegation deployment message and transmits the authorized operation message to the electronic apparatus. The original authorized operation message includes an operation task message and a right level. The electronic apparatus decrypts the authorized operation message into the original authorized operation message by the authorization key included in the second delegation deployment message and performs an operation according to the operation task message and the right level.Type: GrantFiled: January 26, 2015Date of Patent: December 8, 2015Assignee: Institute For Information IndustryInventors: Jui-Ming Wu, You-Lian Huang, Chih-Chiang Hsieh, Emery Jou
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Patent number: 9098994Abstract: An electric meter (EM) network system, an EM node and a broadcasting method thereof are provided. The EM node, which is electrically connected to a power supply loop, stores a layer number and a total layer number. When the power supply loop recovers from a power disconnect condition to a power supplying condition, the EM node obtains a waiting time according to a difference value between the layer number and the total layer number, and broadcasts a route message after the waiting time.Type: GrantFiled: February 27, 2013Date of Patent: August 4, 2015Assignee: Institute For Information IndustryInventors: Chih-Chiang Hsieh, Hsiang-Chin Hsieh, Tien-Yi Sun, Emery Jou
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Publication number: 20150180838Abstract: A major management apparatus, an authorized management apparatus, an electronic apparatus for delegation management, and delegation management methods thereof are provided. The major management apparatus generates a first and a second delegation deployment messages and respectively transmits them to the authorized management apparatus and the electronic apparatus. The authorized management apparatus encrypts an original authorized operation message into an authorized operation message by an authorization key included in the first delegation deployment message and transmits the authorized operation message to the electronic apparatus. The original authorized operation message includes an operation task message and a right level. The electronic apparatus decrypts the authorized operation message into the original authorized operation message by the authorization key included in the second delegation deployment message and performs an operation according to the operation task message and the right level.Type: ApplicationFiled: January 26, 2015Publication date: June 25, 2015Inventors: Jui-Ming WU, You-Lian HUANG, Chih-Chiang HSIEH, Emery JOU