Patents by Inventor Chih-Chieh Chang

Chih-Chieh Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11226589
    Abstract: A holographic image film, and a holographic image recording method and reconstruction method are provided. The holographic image recording method includes a preparation step, an irradiation step and a recording step. The preparation step includes stacking a holographic negative film on a transparent substrate. The irradiation step includes emitting object light and reference light. The reference light is emitted into the transparent substrate and undergoes multiple times of total reflections in a thickness of the transparent substrate to form total internal reflected light. The recording step includes generating a holographic image interference line by a mutual interference between the total internal reflected light and the object light, and recording the holographic image interference line on the holographic negative film in a photosensitive manner.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: January 18, 2022
    Assignee: inFilm Optoelectronic Inc.
    Inventors: Chih-Hsiung Lin, Chih-Chieh Chang
  • Publication number: 20210313190
    Abstract: Methods of manufacturing a chemical-mechanical polishing (CMP) slurry and methods of performing CMP process on a substrate comprising metal features are described herein. The CMP slurry may be manufactured using a balanced concentration ratio of chelator additives to inhibitor additives, the ratio being determined based on an electro potential (Ev) value of a metal material of the substrate. The CMP process may be performed on the substrate based on the balanced concentration ratio of chelator additives to inhibitor additives of the CMP slurry.
    Type: Application
    Filed: June 21, 2021
    Publication date: October 7, 2021
    Inventors: Chun-Hao Kung, Tung-Kai Chen, Chih-Chieh Chang, Kao-Feng Liao, Hui-Chi Huang, Kei-Wei Chen
  • Patent number: 11113232
    Abstract: A computer system includes a processor and a memory. The processor is located on a first circuit board having a first connector. The memory is located on a second circuit board having a second connector. The first circuit board and the second board are physically separated from each other but connect to each other through the connector. The processor and the memory are communicated to each other based on a differential signaling scheme.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: September 7, 2021
    Assignee: SUPER MICRO COMPUTER, INC.
    Inventors: Vivek Joshi, Chih-Chieh Chang, Chang-Hsin Geng
  • Publication number: 20210239902
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a photonic die, an encapsulant and a wave guide structure. The photonic die includes: a substrate, having a wave guide pattern formed at front surface; and a dielectric layer, covering the front surface of the substrate, and having an opening overlapped with an end portion of the wave guide pattern. The encapsulant laterally encapsulates the photonic die. The wave guide structure lies on the encapsulant and the photonic die, and extends into the opening of the dielectric layer, to be optically coupled to the wave guide pattern.
    Type: Application
    Filed: March 28, 2021
    Publication date: August 5, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chieh Chang, Chung-Hao Tsai, Chen-Hua Yu, Chuei-Tang Wang
  • Publication number: 20210202453
    Abstract: A method includes forming multiple photonic devices in a semiconductor wafer, forming a v-shaped groove in a first side of the semiconductor wafer, forming an opening extending through the semiconductor wafer, forming multiple conductive features within the opening, wherein the conductive features extend from the first side of the semiconductor wafer to a second side of the semiconductor wafer, forming a polymer material over the v-shaped groove, depositing a molding material within the opening, wherein the multiple conductive features are separated by the molding material, after depositing the molding material, removing the polymer material to expose the v-shaped groove, and placing an optical fiber within the v-shaped groove.
    Type: Application
    Filed: February 22, 2021
    Publication date: July 1, 2021
    Inventors: Chih-Chieh Chang, Chung-Hao Tsai, Chuei-Tang Wang, Hsing-Kuo Hsia, Chen-Hua Yu
  • Patent number: 11043396
    Abstract: Methods of manufacturing a chemical-mechanical polishing (CMP) slurry and methods of performing CMP process on a substrate comprising metal features are described herein. The CMP slurry may be manufactured using a balanced concentration ratio of chelator additives to inhibitor additives, the ratio being determined based on an electro potential (Ev) value of a metal material of the substrate. The CMP process may be performed on the substrate based on the balanced concentration ratio of chelator additives to inhibitor additives of the CMP slurry.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: June 22, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hao Kung, Tung-Kai Chen, Chih-Chieh Chang, Kao-Feng Liao, Hui-Chi Huang, Kei-Wei Chen
  • Publication number: 20210096310
    Abstract: A package assembly and a manufacturing method thereof are provided. The package assembly includes a first package component and an optical signal port disposed aside the first package component. The first package component includes a first die including an electronic integrated circuit, a first insulating encapsulation laterally covering the first die, a redistribution structure disposed on the first die and the first insulating encapsulation, and a second die including a photonic integrated circuit and electrically coupled to the first die through the redistribution structure. The optical signal port is optically coupled to an edge facet of the second die of the first package component.
    Type: Application
    Filed: May 26, 2020
    Publication date: April 1, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Chieh Chang, Chung-Hao Tsai, Chen-Hua Yu, Chuei-Tang Wang
  • Patent number: 10962711
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a photonic die, an encapsulant and a wave guide structure. The photonic die includes a substrate and a dielectric layer. The substrate has a wave guide pattern. The dielectric layer is disposed over the substrate. The photonic die is encapsulated by the encapsulant. The wave guide structure spans over the front side of the photonic die and a top surface of the encapsulant, and penetrates the dielectric layer to be optically coupled with the wave guide pattern.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: March 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chieh Chang, Chung-Hao Tsai, Chen-Hua Yu, Chuei-Tang Wang
  • Patent number: 10947414
    Abstract: A polishing composition for a chemical mechanical polishing process includes abrasive particles, at least one chemical additive, and a non-aqueous solvent.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: March 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fang-I Chih, Chih-Chieh Chang, Hui-Chi Huang, Kei-Wei Chen
  • Patent number: 10930628
    Abstract: A method includes forming multiple photonic devices in a semiconductor wafer, forming a v-shaped groove in a first side of the semiconductor wafer, forming an opening extending through the semiconductor wafer, forming multiple conductive features within the opening, wherein the conductive features extend from the first side of the semiconductor wafer to a second side of the semiconductor wafer, forming a polymer material over the v-shaped groove, depositing a molding material within the opening, wherein the multiple conductive features are separated by the molding material, after depositing the molding material, removing the polymer material to expose the v-shaped groove, and placing an optical fiber within the v-shaped groove.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: February 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chieh Chang, Chung-Hao Tsai, Chuei-Tang Wang, Hsing-Kuo Hsia, Chen-Hua Yu
  • Publication number: 20200411329
    Abstract: A planarization method and a CMP method are provided. The planarization method includes providing a substrate with a first region and a second region having different degrees of hydrophobicity or hydrophilicity and performing a surface treatment to the first region to render the degrees of hydrophobicity or hydrophilicity in proximity to that of the second region. The CMP method includes providing a substrate with a first region and a second region; providing a polishing slurry on the substrate, wherein the polishing slurry and the surface of the first region have a first contact angle, and the polishing slurry and the surface of the first region have a second contact angle; modifying the surface of the first region to make a contact angle difference between the first contact angle and the second contact angle equal to or less than 30 degrees.
    Type: Application
    Filed: September 12, 2020
    Publication date: December 31, 2020
    Inventors: TUNG-KAI CHEN, CHING-HSIANG TSAI, KAO-FENG LIAO, CHIH-CHIEH CHANG, CHUN-HAO KUNG, FANG-I CHIH, HSIN-YING HO, CHIA-JUNG HSU, HUI-CHI HUANG, KEI-WEI CHEN
  • Patent number: 10777423
    Abstract: A planarization method and a CMP method are provided. The planarization method includes providing a substrate with a first region and a second region having different degrees of hydrophobicity or hydrophilicity and performing a surface treatment to the first region to render the degrees of hydrophobicity or hydrophilicity in proximity to that of the second region. The CMP method includes providing a substrate with a first region and a second region; providing a polishing slurry on the substrate, wherein the polishing slurry and the surface of the first region have a first contact angle, and the polishing slurry and the surface of the first region have a second contact angle; modifying the surface of the first region to make a contact angle difference between the first contact angle and the second contact angle equal to or less than 30 degrees.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: September 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tung-Kai Chen, Ching-Hsiang Tsai, Kao-Feng Liao, Chih-Chieh Chang, Chun-Hao Kung, Fang-I Chih, Hsin-Ying Ho, Chia-Jung Hsu, Hui-Chi Huang, Kei-Wei Chen
  • Publication number: 20200286845
    Abstract: A semiconductor package includes an interconnect structure having a first surface and a second surface opposite to the first surface, an insulating layer contacting the second surface of the interconnect structure wherein the insulating layer has a third surface facing the second surface of the interconnect structure and a fourth surface opposite to the third surface, at least one optical chip over the fourth surface of the insulating layer and electrically coupled to the interconnect structure, and a molding compound over the first surface of the interconnect structure.
    Type: Application
    Filed: May 20, 2020
    Publication date: September 10, 2020
    Inventors: CHUEI-TANG WANG, CHIH-CHIEH CHANG, YU-KUANG LIAO, HSING-KUO HSIA, CHIH-YUAN CHANG, JENG-SHIEN HSIEH, CHEN-HUA YU
  • Publication number: 20200174187
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a photonic die, an encapsulant and a wave guide structure. The photonic die includes a substrate and a dielectric layer. The substrate has a wave guide pattern. The dielectric layer is disposed over the substrate. The photonic die is encapsulated by the encapsulant. The wave guide structure spans over the front side of the photonic die and a top surface of the encapsulant, and penetrates the dielectric layer to be optically coupled with the wave guide pattern.
    Type: Application
    Filed: September 13, 2019
    Publication date: June 4, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Chieh Chang, Chung-Hao Tsai, Chen-Hua Yu, Chuei-Tang Wang
  • Patent number: 10665560
    Abstract: A semiconductor package includes an interconnect structure having a first surface and a second surface opposite to the first surface, at least one optical chip over the first surface of the interconnect structure and electrically coupled to the interconnect structure, an insulating layer contacting the second surface of the interconnect structure, and a molding compound over the first surface of the interconnect structure. The insulating layer includes a third surface facing the second surface of the interconnect structure and a fourth surface opposite to the third surface. At least an edge of the optical chip is covered by the molding compound.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: May 26, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chuei-Tang Wang, Chih-Chieh Chang, Yu-Kuang Liao, Hsing-Kuo Hsia, Chih-Yuan Chang, Jeng-Shien Hsieh, Chen-Hua Yu
  • Publication number: 20200130138
    Abstract: Provided herein are chemical-mechanical planarization (CMP) systems and methods to reduce metal particle pollution on dressing disks and polishing pads. Such methods may include contacting a dressing disk and at least one conductive element with an electrolyte solution and applying direct current (DC) power to the dressing disk and the at least one conductive element.
    Type: Application
    Filed: September 26, 2019
    Publication date: April 30, 2020
    Inventors: Chih-Chieh CHANG, Yen-Ting CHEN, Hui-Chi HUANG, Kei-Wei CHEN
  • Publication number: 20200133913
    Abstract: A computer system includes a processor and a memory. The processor is located on a first circuit board having a first connector. The memory is located on a second circuit board having a second connector. The first circuit board and the second board are physically separated from each other but connect to each other through the connector. The processor and the memory are communicated to each other based on a differential signaling scheme.
    Type: Application
    Filed: October 26, 2018
    Publication date: April 30, 2020
    Inventors: VIVEK JOSHI, CHIH-CHIEH CHANG, CHANG-HSIN GENG
  • Publication number: 20200081399
    Abstract: A holographic image film, and a holographic image recording method and reconstruction method are provided. The holographic image recording method includes a preparation step, an irradiation step and a recording step. The preparation step includes stacking a holographic negative film on a transparent substrate. The irradiation step includes emitting object light and reference light. The reference light is emitted into the transparent substrate and undergoes multiple times of total reflections in a thickness of the transparent substrate to form total internal reflected light. The recording step includes generating a holographic image interference line by a mutual interference between the total internal reflected light and the object light, and recording the holographic image interference line on the holographic negative film in a photosensitive manner.
    Type: Application
    Filed: September 6, 2019
    Publication date: March 12, 2020
    Applicant: inFilm Optoelectronic Inc.
    Inventors: Chih-Hsiung LIN, Chih-Chieh CHANG
  • Publication number: 20200043745
    Abstract: Methods of manufacturing a chemical-mechanical polishing (CMP) slurry and methods of performing CMP process on a substrate comprising metal features are described herein. The CMP slurry may be manufactured using a balanced concentration ratio of chelator additives to inhibitor additives, the ratio being determined based on an electro potential (Ev) value of a metal material of the substrate. The CMP process may be performed on the substrate based on the balanced concentration ratio of chelator additives to inhibitor additives of the CMP slurry.
    Type: Application
    Filed: November 2, 2018
    Publication date: February 6, 2020
    Inventors: Chun-Hao Kung, Tung-Kai Chen, Chih-Chieh Chang, Kao-Feng Liao, Hui-Chi Huang, Kei-Wei Chen
  • Patent number: D912661
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: March 9, 2021
    Assignee: Dell Products L.P.
    Inventors: Eid-Beng Goh, Chih Chieh Chang, An-Chung Hsieh, Chien-Cheng Chen, Kyu Sang Park