Abstract: A polishing composition for a chemical mechanical polishing process includes abrasive particles, at least one chemical additive, and a non-aqueous solvent.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first metal layer over a substrate, forming a dielectric layer over the first metal layer. The method includes forming a trench in the dielectric layer, and performing a surface treatment process on a sidewall surface of the trench to form a hydrophobic layer. The hydrophobic layer is formed on a sidewall surface of the dielectric layer. The method further includes depositing a metal material in the trench and over the hydrophobic layer to form a via structure.

Abstract: A LC lens and a liquid-crystal medium used in said LC lens, wherein the medium contains one or more compounds of each of formulae I and II

Abstract: A method includes forming multiple photonic devices in a semiconductor wafer, forming a v-shaped groove in a first side of the semiconductor wafer, forming an opening extending through the semiconductor wafer, forming multiple conductive features within the opening, wherein the conductive features extend from the first side of the semiconductor wafer to a second side of the semiconductor wafer, forming a polymer material over the v-shaped groove, depositing a molding material within the opening, wherein the multiple conductive features are separated by the molding material, after depositing the molding material, removing the polymer material to expose the v-shaped groove, and placing an optical fiber within the v-shaped groove.

Abstract: In an embodiment, a method includes: forming an interconnect including waveguides and conductive features disposed in a plurality of dielectric layers, the conductive features including conductive lines and vias, the waveguides formed of a first material having a first refractive index, the dielectric layers formed of a second material having a second refractive index less than the first refractive index; bonding a plurality of dies to a first side of the interconnect, the dies electrically connected by the conductive features, the dies optically connected by the waveguides; and forming a plurality of conductive connectors on a second side of the interconnect, the conductive connectors electrically connected to the dies by the conductive features.

Abstract: In an embodiment, a method includes: forming an interconnect including waveguides and conductive features disposed in a plurality of dielectric layers, the conductive features including conductive lines and vias, the waveguides formed of a first material having a first refractive index, the dielectric layers formed of a second material having a second refractive index less than the first refractive index; bonding a plurality of dies to a first side of the interconnect, the dies electrically connected by the conductive features, the dies optically connected by the waveguides; and forming a plurality of conductive connectors on a second side of the interconnect, the conductive connectors electrically connected to the dies by the conductive features.

Abstract: A planarization method and a CMP method are provided. The planarization method includes providing a substrate with a first region and a second region having different degrees of hydrophobicity or hydrophilicity and performing a surface treatment to the first region to render the degrees of hydrophobicity or hydrophilicity in proximity to that of the second region. The CMP method includes providing a substrate with a first region and a second region; providing a polishing slurry on the substrate, wherein the polishing slurry and the surface of the first region have a first contact angle, and the polishing slurry and the surface of the first region have a second contact angle; modifying the surface of the first region to make a contact angle difference between the first contact angle and the second contact angle equal to or less than 30 degrees.

Abstract: A semiconductor package includes an interconnect structure having a first surface and a second surface opposite to the first surface, at least one optical chip over the first surface of the interconnect structure and electrically coupled to the interconnect structure, an insulating layer contacting the second surface of the interconnect structure, and a molding compound over the first surface of the interconnect structure. The insulating layer includes a third surface facing the second surface of the interconnect structure and a fourth surface opposite to the third surface. At least an edge of the optical chip is covered by the molding compound.

Abstract: In an embodiment, a method includes: forming an interconnect including waveguides and conductive features disposed in a plurality of dielectric layers, the conductive features including conductive lines and vias, the waveguides formed of a first material having a first refractive index, the dielectric layers formed of a second material having a second refractive index less than the first refractive index; bonding a plurality of dies to a first side of the interconnect, the dies electrically connected by the conductive features, the dies optically connected by the waveguides; and forming a plurality of conductive connectors on a second side of the interconnect, the conductive connectors electrically connected to the dies by the conductive features.

Abstract: A solid-state imaging device includes a substrate containing a plurality of photoelectric conversion elements arranged into a pixel array. A color filter layer including a plurality of color filter segments is disposed above the photoelectric conversion elements. A partition grid includes a plurality of partitions, and each of the partitions is disposed between two adjacent color filter segments. The color filter layer and the partition grid are disposed in the same layer. In addition, the partitions include a first partition disposed at a center line of the pixel array and a second partition disposed at an edge of the pixel array. The second partition has a top width that is larger than the top width of the first partition.

Abstract: A solid-state imaging device includes a substrate containing a plurality of photoelectric conversion elements arranged into a pixel array. A color filter layer including a plurality of color filter segments is disposed above the photoelectric conversion elements. A partition grid includes a plurality of partitions, and each of the partitions is disposed between two adjacent color filter segments. The color filter layer and the partition grid are disposed in the same layer. In addition, the partitions include a first partition disposed at a center line of the pixel array and a second partition disposed at an edge of the pixel array. The second partition has a top width that is larger than the top width of the first partition.

Abstract: A method for fabricating a semiconductor device includes forming a relaxed semiconductor layer on a substrate, the substrate comprising an n-type region and a p-type region. The method further includes forming a tensile strained semiconductor layer on the relaxed semiconductor layer, etching a portion of the tensile strained semiconductor layer in the p-type region, forming a compressive strained semiconductor layer on the tensile strained semiconductor layer in the p-type region, forming a first gate in the n-type region and a second gate in the p-type region, and forming a first set of source/drain features adjacent to the first gate and a second set of source/drain features adjacent to the second gate. The second set of source/drain features are deeper than the first set of source/drain features.

Abstract: A method of dynamic random access memory (DRAM) resource control for a DRAM manager of an electronic device is disclosed. The method comprises receiving at least one respective request message from at least one DARM user of the electronic device, each request message indicating required power information requested by the DRAM user sending the request message, and determining the DRAM to operate in one of a plurality of predetermined DRAM resource statuses respectively corresponding to a plurality of power levels according to the required power information respectively indicated by the at least one request message.

Abstract: An electrical connector structure includes a housing and signal modules mounted therein. Each signal module includes an insulating body, conductive terminals and a ground shield. The insulating body has a first side having a guide projection, and a second side opposite to the first side and having a guide groove. When a first signal module has been mounted in the housing, a second signal module is guided and moved to mount into the housing by the guide groove of the second signal module receiving the guide projection of the first signal module, or by the guide projection of the second signal module sliding into the guide groove of the first signal module, whereby reducing relative movement between signal modules in the housing. The signal modules may be mounted one by one in the housing, or may be stacked side by side and then mounted in the housing as a whole.

Abstract: A method and an apparatus for performing power consumption management are provided, where the method is applied to an electronic device. The method includes: obtaining current information corresponding to an application from a database, the current information being of at least one current on at least one current path between a battery and at least one portion of the electronic device; and performing battery drain prediction corresponding to the application according to the current information. The method may further include: performing sampling operations to generate a plurality of samples of the current, and more particularly, utilizing an ADC to perform analog-to-digital conversion on a voltage difference corresponding to the current to generate the plurality of samples. The voltage difference can be obtained by probing two terminals of a resistor or a Hall component.

Abstract: An electrical connector structure includes a housing and signal modules mounted therein. Each signal module includes an insulating body, conductive terminals and a ground shield. The insulating body has a first side having a guide projection, and a second side opposite to the first side and having a guide groove. When a first signal module has been mounted in the housing, a second signal module is guided and moved to mount into the housing by the guide groove of the second signal module receiving the guide projection of the first signal module, or by the guide projection of the second signal module sliding into the guide groove of the first signal module, whereby reducing relative movement between signal modules in the housing. The signal modules may be mounted one by one in the housing, or may be stacked side by side and then mounted in the housing as a whole.

Abstract: The present disclosure relates to a touch-control type keyboard. The touch-control type keyboard includes a cover board and a touch module. The cover board includes a first surface and a second surface. The cover board defines a number of keys on the first surface, and at least one of the keys is a function key. The touch-control module is located on the second surface of the cover board. The touch-control module comprises at least two conductive films and an integrated circuit. The at least two conductive films are coplanar and spaced from each other. The at least one function key is independently located at a position corresponding to one of the at least two conductive films. Each of the at least two conductive films is independently electrically connected to the integrated circuit.

Abstract: A touch panel includes an insulated substrate including a planar part and a folded part extending from the planar part; a transparent conductive layer located on the planar part and the folded part; a plurality of planar electrodes located on the planar part and electrically connected to the transparent conductive layer; and at least one side electrode located on the folded part and electrically connected to the transparent conductive layer on the folded part. The planar electrodes, the transparent conductive layer and the planar part are formed into a planar touch module configured to detect a planar input signal resulted from the planar part. The at least one side electrode the folded part and the transparent conductive layer on the folded part are formed into a side touch module configured to sense a side input signal resulted from at least one virtual key corresponding the at least one side electrode.