Abstract: A flyback power converter includes a power transformer, a first lossless voltage conversion circuit, a first low-dropout linear regulator and a secondary side power supply circuit. The first low-dropout linear regulator (LDO) generates a first operation voltage as power supply for being supplied to a sub-operation circuit. The secondary side power supply circuit includes a second lossless voltage conversion circuit and a second LDO. The second LDO generates a second operation voltage. The first operation voltage and the second operation voltage are shunted to a common node. When a first lossless conversion voltage is greater than a first threshold voltage, the second LDO is enabled to generate the second operation voltage to replace the first operation voltage as power supply supplied to the sub-operation circuit; wherein the second lossless conversion voltage is lower than the first lossless switching voltage.

Abstract: A display panel including a circuit board, a plurality of bonding pads, a plurality of light emitting devices, and a plurality of solder patterns is provided. The bonding pads are disposed on the circuit board, and each includes a first metal layer and a second metal layer. The second metal layer is located between the first metal layer and the circuit board. The first metal layer includes an opening overlapping the second metal layer. A material of the first metal layer is different from a material of the second metal layer. The light emitting devices are electrically bonded to the bonding pads. Each of the solder patterns electrically connects one of the light emitting devices and one of the bonding pads. The solder patterns each contact the second metal layer through the opening of the first metal layer of one of the bonding pads to form a eutectic bonding.

Abstract: A display driver circuit for controlling a display panel having a plurality of light-emission diode (LED) strings includes a plurality of current regulators and a control circuit. Each of the plurality of current regulators is configured to control one of the plurality of LED strings. The control circuit, coupled to the plurality of current regulators, is configured to generate a plurality of pulses in a plurality of pulse width modulation (PWM) signals and output each of the plurality of PWM signals to a respective current regulator among the plurality of current regulators. Wherein, the plurality of pulses are scrambled.

Abstract: A laser automatic compensation control device includes a controller, a digital array, a decoder, a compensation array and a synchronizer. The controller is configured for receiving a number of laser energy signals and comparing each laser energy signal with a corresponding preset energy value to obtain a corresponding output digital signal. The digital array is electrically connected to the controller and configured for storing the output digital signals. The decoder is electrically connected to the digital array and configured for converting the output digital signals into a number of analog compensation signals. The compensation array is electrically connected to the decoder and configured for storing the analog compensation signals. The synchronizer is electrically connected to the compensation array and configured for receiving the analog compensation signals, and synchronously outputting the analog compensation signals to a laser diode array.

Abstract: A heterogeneous integration semiconductor package structure including a heat dissipation assembly, multiple chips, a package assembly, multiple connectors and a circuit substrate is provided. The heat dissipation assembly has a connection surface and includes a two-phase flow heat dissipation device and a first redistribution structure layer embedded in the connection surface. The chips are disposed on the connection surface of the heat dissipation assembly and electrically connected to the first redistribution structure layer. The package assembly surrounds the chips and includes a second redistribution structure layer disposed on a lower surface and multiple conductive vias electrically connected to the first redistribution structure layer and the second redistribution structure layer. The connectors are disposed on the package assembly and electrically connected to the second redistribution structure layer.

Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.

Abstract: This disclosure relates to a surgical tool configured for holding an implant includes an inner rod and a sleeve. The inner rod includes a rod portion and a holding portion. The holding portion is located at one end of the rod portion and has a first accommodation space configured for accommodating at least part of the implant. The sleeve includes a sleeving portion and a retaining portion. The sleeving portion is slidably sleeved on the rod portion of the inner rod. The retaining portion is located at one end of the sleeving portion and selectively presses against the holding portion. The inner rod further includes at least one fin portion protruded from the holding portion and located in the first accommodation space for being inserted into at least one slot of the implant.

Abstract: A device includes a diffraction-based overlay (DBO) mark having an upper-layer pattern disposed over a lower-layer pattern, and having smallest dimension greater than about 5 micrometers. The device further includes a calibration mark having an upper-layer pattern disposed over a lower-layer pattern, positioned substantially at a center of the DBO mark, and having smallest dimension less than about 1/5 the size of the smallest dimension of the DBO mark.

Abstract: A computer-implemented method for executing a computation task in a molecular dynamic simulation includes identifying a bonding target on a ligand; constructing a protein structure; rendering an image of the ligand; subsampling data pertaining to the constructed protein structure and the image of the ligand at a particular frequency; rendering a two-dimensional image of the constructed protein structure relative to the ligand from a plurality of viewpoints; computing optical flows of the protein structure relative to the ligand based on the two-dimensional image; analyzing the optical flows to determine a displacement of atoms; simulating a binding state outcome of the protein structure relative to the ligand for each of the plurality of viewpoints; and predicting a probability of the protein structure binding with the ligand, based on the predicted binding state outcome for each of the plurality of viewpoints.

Abstract: Original data for machine learning training can be received. The original data can be divided into baseline data and difference data. The baseline data and the difference data can be stored in different memory devices of the memory hierarchy associated with a computer, wherein the baseline data is stored in a first memory device having faster access speed than a second memory device in which the difference data is stored. The baseline data and the difference data can be loaded from the different memory devices. The original data can be reconstructed from the baseline data and the difference data. The reconstructed original data can be fed to a machine learning model to train the machine learning model.

Abstract: Altering protein-ligand structures by generating molecular trajectory data for a protein-ligand structure, determining a molecular level binding affinity according to the molecular trajectory data, determining an atom level binding affinity for a first atom of the protein-ligand structure according to the molecular trajectory data, determining a correlation between the atom level and the molecular level binding affinities, and altering the protein-ligand structure according to the correlation.

Abstract: Semiconductor processing apparatuses and methods are provided in which a semiconductor wafer is flipped and then rotated between patterning of front and back sides of the semiconductor wafer by first and second reticles, respectively. In some embodiments, a method includes patterning, by a first reticle, a first layer on a first side of a semiconductor wafer while the first side of the semiconductor wafer is facing a first direction. The semiconductor wafer is then flipped. A second side of the semiconductor wafer that is opposite the first side faces the first direction after the flipping the semiconductor wafer. The semiconductor wafer is then rotated about a rotational axis extending along the first direction, and a second layer on the second side of the semiconductor wafer is patterned by a second reticle.

Abstract: Semiconductor processing apparatuses and methods are provided in which a semiconductor wafer is flipped and then rotated between patterning of front and back sides of the semiconductor wafer by first and second reticles, respectively. In some embodiments, a method includes patterning, by a first reticle, a first layer on a first side of a semiconductor wafer while the first side of the semiconductor wafer is facing a first direction. The semiconductor wafer is then flipped. A second side of the semiconductor wafer that is opposite the first side faces the first direction after the flipping the semiconductor wafer. The semiconductor wafer is then rotated about a rotational axis extending along the first direction, and a second layer on the second side of the semiconductor wafer is patterned by a second reticle.

Abstract: Original data for machine learning training can be received. The original data can be divided into baseline data and difference data. The baseline data and the difference data can be stored in different memory devices of the memory hierarchy associated with a computer, wherein the baseline data is stored in a first memory device having faster access speed than a second memory device in which the difference data is stored. The baseline data and the difference data can be loaded from the different memory devices. The original data can be reconstructed from the baseline data and the difference data. The reconstructed original data can be fed to a machine learning model to train the machine learning model.

Abstract: A data index sequence indexing a dataset is received. A location of a data sample identified by a data index in the data index sequence is determined. A scheme is generated for specifying a data movement based on the location. Responsive to determining that the location is a cache of a process, the data sample in the cache can be reused without having to load the data sample from a storage device.

Abstract: A digital-to-analog converter (DAC) device includes a current-steering DAC circuitry and a calibration circuitry. The current-steering DAC circuitry generates a first signal according to multiple least significant bits of an input signal, and generates a second signal according to multiple most significant bits of the input signal. The calibration circuitry performs a non-binary search algorithm to generate a calibration signal in response to a comparison result of the first signal and the second signal, in order to calibrate the current-steering DAC circuitry according to the calibration signal.

Abstract: A digital-to-analog converter (DAC) device includes a current-steering DAC circuitry and a calibration circuitry. The current-steering DAC circuitry generates a first signal according to multiple least significant bits of an input signal, and generates a second signal according to multiple most significant bits of the input signal. The calibration circuitry performs a non-binary search algorithm to generate a calibration signal in response to a comparison result of the first signal and the second signal, in order to calibrate the current-steering DAC circuitry according to the calibration signal.

Abstract: A data index sequence indexing a dataset is received. A location of a data sample identified by a data index in the data index sequence is determined. A scheme is generated for specifying a data movement based on the location. Responsive to determining that the location is a cache of a process, the data sample in the cache can be reused without having to load the data sample from a storage device.

Abstract: A digital-to-analog converter (DAC) device includes a DAC circuitry and a calibration circuitry. The DAC circuitry generates a first signal according to least significant bits of an input signal, and generates a second signal according to most significant bits of the input signal. The calibration circuitry compares the first signal with the second signal to generate a calibration signal, and calibrates the DAC circuitry according to the calibration signal. The calibration signal has bits. The calibration circuitry further repeatedly compares the first signal and the second signal to generate a plurality of comparison results when determining at least one bit of the bits, and performs a statistic operation according to the comparison results, in order to adjust the at least one bit, and a number of the at least one bit is less than a number of the bits.

Abstract: Provided is a composite electrode material. The composite electrode material is disposed on a surface of an electrode. The composite electrode material includes a plurality of conductive material layers and a plurality of active material layers. The conductive material layers and the active material layers are alternately stacked along a direction non-parallel to the surface of the electrode, and are arranged disorderly along a direction parallel to the surface of the electrode.