Abstract: A method for forming a self-aligned low temperature polysilicon thin film transistor (LTPS TFT). First, active layers of a N type LTPS TFT (NLTPS TFT) and a P type LTPS TFT (PLTPS TFT) are formed on a substrate, and a gate insulating (GI) layer is formed on the substrate. Then, a source electrode, a drain electrode, and lightly doped drains (LDD) of the NLTPS TFT are formed. Further, gate electrodes of the NLTPS TFT and the PLTPS TFT are formed on the gate insulating layer. Finally, the gate electrode of the PLTPS TFT is utilized to form a source electrode and a drain electrode in the active layer of the PLTPS TFT.

Abstract: A method for forming a self-aligned low temperature polysilicon thin film transistor (LTPS TFT). First, active layers of a N type LTPS TFT (NLTPS TFT) and a P type LTPS TFT (PLTPS TFT) are formed on a substrate, and a gate insulating (GI) layer is formed on the substrate. Then, a source electrode, a drain electrode, and lightly doped drains (LDD) of the NLTPS TFT are formed. Further, gate electrodes of the NLTPS TFT and the PLTPS TFT are formed on the gate insulating layer. Finally, the gate electrode of the PLTPS TFT is utilized to form a source electrode and a drain electrode in the active layer of the PLTPS TFT.

Abstract: A capacitor structure includes a first conductive layer, a first insulating layer disposed on a substrate in sequence, a second conductive layer disposed on portions of the first insulating layer, a second insulating layer disposed on the second conductive layer and the first insulating layer, a third conductive layer disposed on portions of the second insulating layer, a third insulating layer disposed on the third conductive layer and the second insulating layer, and a fourth conductive layer disposed on the third insulating layer. The third conductive layer and the fourth conductive layer are electrically connected to the first conductive layer and the second conductive layer through at least one first contact hole adjacent to the second conductive layer and at least one second contact hole, respectively.

Abstract: A method of manufacturing a low temperature polysilicon film is provided. A first metal layer is formed on a substrate; and openings have been formed in the first metal layer. A second metal layer is formed on the first metal layer: and a hole corresponding to each of the openings is formed in the second metal layer. A silicon layer is formed on the second metal layer; a silicon seed is formed on the substrate inside each of the holes. After removing the first and the second metal layers, an amorphous silicon layer is formed on the substrate by using the silicon seed. Then a laser crystallization step is performed to form a polysilicon layer from the amorphous layer. Since the position of the silicon seed can be controlled, the size and distribution of the silicon grain and the number of the silicon crystal interface can also be controlled.

Abstract: A method of forming a CMOS thin film transistor device. A dry etching procedure is performed to remove part of a photoresist layer and part of a metal layer and thus forms a gate with a symmetrical cone shape and a remaining photoresist layer. The dielectric layer is thus exposed in the lightly doped area. Specially, the bottom width of the first gate is narrower than that of the first metal layer and the symmetrical cone shape is gradually thinner from bottom to top. Using the gate as a mask, an n−-ion implantation is performed to form a self-aligned and symmetrical LDD region in a semiconductor layer without additional photolithography steps.

Abstract: A method for forming a self-aligned low temperature polysilicon thin film transistor (LTPS TFT). First, active layers of a N type LTPS TFT (NLTPS TFT) and a P type LTPS TFT (PLTPS TFT) are formed on a substrate, and a gate insulating (GI) layer is formed on the substrate. Then, a source electrode, a drain electrode, and lightly doped drains (LDD) of the NLTPS TFT are formed. Further, gate electrodes of the NLTPS TFT and the PLTPS TFT are formed on the gate insulating layer. Finally, the gate electrode of the PLTPS TFT is utilized to form a source electrode and a drain electrode in the active layer of the PLTPS TFT.

Abstract: A method of forming emitter tips for use in a field emission display. A dielectric layer, an insulating layer, and a conductor layer are formed on a substrate in sequence. An annular groove is formed the conductive layer and the insulating layer. A tip cavity with an insulating tip within is formed by isotropic wet etching. A molybdenum metal layer is formed on the insulating tip. The method of the present invention can substantially reduce the consumption of molybdenum.

Abstract: A mask for fabricating contacts is provided. The mask has a contact pattern with an edge pattern around the edge of the contact pattern. The edge pattern is a half-tone region. Due to the half-tone edge pattern on the mask, contact angle between the sidewall of the contact opening and an underlying conductive layer after a patterning process is reduced.

Abstract: an FED cathode plate with internal via includes an internal via; a second dielectric layer; a second gate line; a metal layer 12 covering the gate line and the internal via; and a contact. The internal via is located on a typical tape line. The second dielectric layer is located on the tape line and abutted against the internal via, thereby connecting to an anode by an adhesive. The second gate line is located on the second dielectric layer and abutted against the internal via. The metal layer is covered over the first gate line, the internal via, and the second gate line; and the contact is located on the tape line and connected adjacent to the second dielectric layer, thereby electrically connecting a lead to outside.

Abstract: A holding stand for fragile plates comprises two hold frames, at least two spacing rods and at least a lateral protect cage and/or a lower protect cage. The hold frames have hollow portions and are disposed to space apart from each other oppositely. The two spacing rods are arranged between the hold frames with two ends of each of the spacing rods being fixedly attached to the two hold frames. The respective spacing rod provides a rod section with spacing pieces being arranged thereon. The lateral protect cage and/or a lower protect cage at both ends thereof being joined to the hold frames and each protect cage has a non-solid buffering enclosure. Once each of the fragile plates is placed between any two of the spacing pieces, the respective fragile plate can keep tight contact with the lateral cages and/or the lower cage.

Abstract: A method of forming emitter tips for use in a field emission display. A dielectric layer, an insulating layer, and a conductor layer are formed on a substrate in sequence. An annular groove is formed the conductive layer and the insulating layer. A tip cavity with an insulating tip within is formed by isotropic wet etching. A molybdenum metal layer is formed on the insulating tip. The method of the present invention can substantially reduce the consumption of molybdenum.

Abstract: A holding stand for fragile plates comprises two hold frames, at least two spacing rods and at least a lateral protect cage and/or a lower protect cage. The hold frames have hollow portions and are disposed to space apart from each other oppositely. The two spacing rods are arranged between the hold frames with two ends of each of the spacing rods being fixedly attached to the two hold frames. The respective spacing rod provides a rod section with spacing pieces being arranged thereon. The lateral protect cage and/or a lower protect cage at both ends thereof being joined to the hold frames and each protect cage has a non-solid buffering enclosure. Once each of the fragile plates is placed between any two of the spacing pieces, the respective fragile plate can keep tight contact with the lateral cages and/or the lower cage.

Abstract: an FED cathode plate with internal via includes an internal via; a second dielectric layer; a second gate line; a metal layer 12 covering the gate line and the internal via; and a contact. The internal via is located on a typical tape line. The second dielectric layer is located on the tape line and abutted against the internal via, thereby connecting to an anode by an adhesive. The second gate line is located on the second dielectric layer and abutted against the internal via. The metal layer is covered over the first gate line, the internal via, and the second gate line; and the contact is located on the tape line and connected adjacent to the second dielectric layer, thereby electrically connecting a lead to outside.

Abstract: A method of manufacturing a hot-stamped decal includes seven steps which are: step (a): to prepare a metalized polyester film comprising a metalized layer disposed on a top surface thereof, a clear polyester sheet disposed to an under side of the metalized layer, an adhesive layer disposed to an under side of the clear polyester sheet and a release sheet disposed to an under side of the adhesive layer; step (b): to prepare crystallized particles; step (c): to add the crystallized particles into a volatile solution to let the crystallized particles in the volatile solution be in an over-saturated status; step (d): to add ink into the over-saturated solution of step (c); step (e): to use the solution of step (d) to execute a printing process on the metalized layer to form a pattern thereon composed of a printed ink layer; step (f): to mop the printed ink layer with an alkaline corrosive solution to corrode the top surface of the metalized layer not covered by the printing ink layer; and step g): a neutralizatio