Abstract: An electronic device including a metal casing and at least one antenna module is provided. The metal casing includes at least one window. The at least one antenna module is disposed in the at least one window. The at least one antenna module includes a first radiator and a second radiator. The first radiator includes a feeding end, a first ground end joined to the metal casing, a second ground end, a first portion extending from the feeding end to the first ground end, and a second portion extending from the feeding end to the second ground end. A first coupling gap is between the second radiator and the first portion. A second coupling gap is between at least part of the second radiator and the metal casing, and the second radiator includes a third ground end joined to the metal casing.

Abstract: An antenna module includes a first metal plate and a frame body. The frame body surrounds the first metal plate. The frame body includes a first antenna radiator, a second antenna radiator, a third antenna radiator, a first breakpoint and a second breakpoint. The first antenna radiator includes a first feeding end and excites a first frequency band. The second antenna radiator includes a second feeding end and excites a second frequency band. The third antenna radiator includes a third feeding end and excites a third frequency band. The first breakpoint is located between the first antenna radiator and the second antenna radiator. The second breakpoint is located between the second antenna radiator and the third antenna radiator. An electronic device including the above-mentioned antenna module is also provided.

Abstract: An electronic device including a bracket and an antenna is provided. The bracket includes first, second, third, and fourth surfaces. The antenna includes a radiator. The radiator includes first, second, third, and fourth portions. The first portion is located on the first surface and includes connected first and second sections. The second portion is located on the second surface and includes third, fourth, fifth, and sixth sections. The third section, the fourth section, and the fifth sections are bent and connected to form a U shape. The third portion is located on the third surface and is connected to the second section and the fourth section. The fourth portion is located on the fourth surface and is connected to the fifth section, the sixth section, and the third portion. The radiator is adapted to resonate at a low frequency band and a first high frequency band.

Abstract: A bonding pad such as for a ball grid array includes a conductive pad having a top surface and a first interface surface in contact with a signal trace of a substrate, and a plating layer having a bottom surface in direct contact with the top surface of the conductive pad. The plating layer includes one or more protrusions extending toward the signal trace in a direction generally parallel to a longitudinal axis of the signal trace. Each of the one or more protrusions includes two parallel sidewalls extending upwardly from the bottom surface of the plating layer, and a second interface surface contiguous with the bottom surface of the plating layer. The second interface surface is positioned over and in direct contact with a top surface of the signal trace. The protrusions prevent the connection to the signal trace from being compromised.

Abstract: A bonding pad such as for a ball grid array includes a conductive pad having a top surface and a first interface surface in contact with a signal trace of a substrate, and a plating layer having a bottom surface in direct contact with the top surface of the conductive pad. The plating layer includes one or more protrusions extending toward the signal trace in a direction generally parallel to a longitudinal axis of the signal trace. Each of the one or more protrusions includes two parallel sidewalls extending upwardly from the bottom surface of the plating layer, and a second interface surface contiguous with the bottom surface of the plating layer. The second interface surface is positioned over and in direct contact with a top surface of the signal trace. The protrusions prevent the connection to the signal trace from being compromised.

Abstract: A memory card includes a memory card body dimensioned to house at least one integrated circuit die package. The memory card body, in certain embodiments, includes a first surface spaced apart from a second surface and a plurality of side surfaces connecting the first surface to the second surface. The memory card also includes a contact pad disposed on at least one side surface of the plurality of side surfaces. The contact pad includes a first conductive layer, a second conductive layer, and an insulating layer disposed between the first conductive layer and the second conductive layer.

Abstract: Devices and methods are described for reducing etching due to galvanic effect within a printed circuit board that may be used, for example, in a data storage device, such as a card-type data storage device. Specifically, a contact trace is coupled to a contact finger that has a substantially larger surface area than the contact trance, and that is configured to couple the data storage device to a host device. The contact trace is electrically isolated from the rest of the circuitry during a fabrication process. The contact finger and an exposed portion of the contact trace are plated with a common material to reduce galvanic etching of the contact trace during fabrication. The contact trace is then connected to an impedance trace though at least one of a component and a bond wire.

Abstract: A memory card includes a memory card body dimensioned to house at least one integrated circuit die package. The memory card body, in certain embodiments, includes a first surface spaced apart from a second surface and a plurality of side surfaces connecting the first surface to the second surface. The memory card also includes a contact pad disposed on at least one side surface of the plurality of side surfaces. The contact pad includes a first conductive layer, a second conductive layer, and an insulating layer disposed between the first conductive layer and the second conductive layer.

Abstract: A semiconductor device including control switches enabling a semiconductor die in a stack of semiconductor die to send or receive a signal, while electrically isolating the remaining die in the die stack. Parasitic pin cap is reduced or avoided by electrically isolating the non-enabled semiconductor die in the die stack.

Abstract: A semiconductor device is disclosed including a stack of semiconductor die on a substrate, wherein a semiconductor die in the stack is wire bonded to the substrate using dummy wire bonds. Each dummy wire bond has a stiffness so that together, the dummy wire bonds effectively pull and/or hold down the die stack against the substrate.

Abstract: A device may include a fan-out structure that has a plurality of integrated circuits. The integrated circuits may be of different types, such as by being configured differently or configured to perform different functions. The fan-out structure may be coupled to another integrated circuit structure, such as a die stack. For example, the fan-out structure may be coupled to a top surface or a bottom surface of the integrated circuit structure, or may otherwise be disposed within a vertical profile defined by the integrated circuit structure. Horizontally-extending and vertically-extending paths may be disposed in between and around the combined fan-out structure and integrated circuit structure to enable the integrated circuits of the two structures to communicate.

Abstract: A semiconductor device is disclosed including a stack of semiconductor die on a substrate, wherein a semiconductor die in the stack is wire bonded to the substrate using dummy wire bonds. Each dummy wire bond has a stiffness so that together, the dummy wire bonds effectively pull and/or hold down the die stack against the substrate.

Abstract: A semiconductor device is disclosed including semiconductor die formed with functionally redundant main and optional die bond pads. In examples, the optional die bond pad is configured to be optionally redundant to the main die bond pad by forming the optional die bond pad with first and second electrically isolated portions, and electrically interconnecting the main die bond pad with the first portion of the second die bond pad. The second die bond pad may or may not be made redundant to the first die bond pad depending on whether an electrically conductive material is deposited on the first and second portions of the optional die bond pad.

Abstract: A wide I/O semiconductor device is disclosed including a memory die stack wire bonded to an interface chip. The stack of memory die may be wire bonded to the interface chip using a wire bond scheme optimized for die-to-die connection and optimized for the large number of wire bond connections in a wide I/O semiconductor device. This method can achieve significant BW increase by improving packaging yield and costs, not possible with current packaging schemes.

Abstract: A semiconductor device, and a method of its manufacture, are disclosed. The semiconductor device includes a substrate having a solder mask. A plurality of pillar bases are formed on the solder mask, and a plurality of solder pillars are applied to the pillar bases. The plurality of solder pillars support one or more semiconductor die above the substrate and the number of solder pillars prevent stresses in the one or more semiconductor die which could otherwise damage the semiconductor die.

Abstract: A semiconductor device including control switches enabling a semiconductor die in a stack of semiconductor die to send or receive a signal, while electrically isolating the remaining die in the die stack. Parasitic pin cap is reduced or avoided by electrically isolating the non-enabled semiconductor die in the die stack.

Abstract: A device may include a fan-out structure that has a plurality of integrated circuits. The integrated circuits may be of different types, such as by being configured differently or configured to perform different functions. The fan-out structure may be coupled to another integrated circuit structure, such as a die stack. For example, the fan-out structure may be coupled to a top surface or a bottom surface of the integrated circuit structure, or may otherwise be disposed within a vertical profile defined by the integrated circuit structure. Horizontally-extending and vertically-extending paths may be disposed in between and around the combined fan-out structure and integrated circuit structure to enable the integrated circuits of the two structures to communicate.

Abstract: A printed circuit board is disclosed having coextensive electrical connectors and contact pad areas. Areas of the contact pads where the traces and/or vias are located may be etched away to ensure electrical isolation between the traces, vias and contact pads.

Abstract: A wide I/O semiconductor device is disclosed including a memory die stack wire bonded to an interface chip. The stack of memory die may be wire bonded to the interface chip using a wire bond scheme optimized for die-to-die connection and optimized for the large number of wire bond connections in a wide I/O semiconductor device. This method can achieve significant BW increase by improving packaging yield and costs, not possible with current packaging schemes.

Abstract: A wide I/O semiconductor device is disclosed including a memory die stack wire bonded to an interface chip. The stack of memory die may be wire bonded to the interface chip using a wire bond scheme optimized for die-to-die connection and optimized for the large number of wire bond connections in a wide I/O semiconductor device. This method can achieve significant BW increase by improving packaging yield and costs, not possible with current packaging schemes.