Abstract: A semiconductor device and a fabrication method of the same are proposed, in which at least one electronic component is firstly mounted on a first substrate, and then the first substrate is attached onto a semiconductor chip or a second substrate. Further, with the chip being deposited on the second substrate, electrical connection is established among the first substrate, the second substrate and the chip. This combined structure is subsequently subjected to molding, ball implantation and singulation processes, and thus completes the fabrication of the semiconductor device. Such a semiconductor device provides significant advantages, including prevention of the occurrence of wire short-circuiting, no need to alter the substrate design, no need to use a circuit pattern with fine pitches or an expensive substrate integrated with electronic components.

Abstract: A semiconductor package is proposed, in which a substrate is formed with a chip bonding area and a plurality of bond fingers surrounding the chip bonding area, and a plurality of bridging elements are disposed in a stagger manner between the chip bonding area and the bond fingers on the substrate. Multiple wire bonding processes are performed to bond first gold wires between the chip and the bridging elements, and bond second gold wires between the bridging elements and the bond fingers. This therefore significantly shortens a wire bonding distance as compared with only one time of wire bonding for electrically connecting the chip to the substrate. As a result, wire bond operability is improved, and the shortened wire bonding distance reduces wire length so as to enhance resistance of the gold wires to mold flow impact during molding, thereby preventing wire sweeping or wire sagging from occurrence.

Abstract: A method is proposed for fabricating a substrate-based semiconductor package without mold flash. The proposed method is characterized by the provision of one or more dummy traces between each overly-spaced pair of signal traces that might cause mold flash in subsequent molding process, so that the solder mask covering over these traces can be made substantially planarized in its top surface without the undesired forming of a recessed portion that would otherwise cause leakage of molding material to the outside of the molding region during molding process. Owing to the provision of these dummy traces, no leakage hole would exist between the molding tool and the solder mask, thus preventing mold flash. The proposed method therefore allows the finished semiconductor package to be more assured in quality.

Abstract: A method for electrically connecting a semiconductor chip to solder balls on a BGA (Ball Grid Array) package is proposed. The proposed method is characterized by the use of an electrically-conductive bridge to span in an overhead manner across a continuous electrically-conductive trace that is interposed between a corresponding pair of bond finger and via. The electrically-conductive bridge can be either a gold wire bonded through existing wire-bonding process, or a zero-resistance chip resistor bonded through existing surface-mount technology (SMT). Conventionally, the interposing trace can be bypassed by using a multi-layer substrate. By the proposed method, however, it can be implemented on existing single-layer substrate without having to use multi-layer substrate, and which can be implemented by using existing technology, such as wire-bonding technology or surface-mounting technology, without having to employ more expensive and advanced technologies.

Abstract: An integrated-circuit package with a quick-to-count finger layout design on substrate is proposed, which can help fabrication engineers to visually check the total number of fingers on the substrate in a quick and accurate manner. The proposed integrated-circuit package is characterized by the provision of a line-up array of fingers which includes a plurality of first-shape fingers partitioned equally in number into a plurality of subgroups; and a plurality of second-shape fingers, which are substantially visually distinguishable in outer appearance from the first-shape fingers, and which are interposed between adjacent subgroups of the first-shape fingers to serve as count tokens. This finger layout design allows the fabrication engineers to visually check the total number of the line-up array of fingers on the substrate simply by counting through the second-shape fingers that serve as count tokens and then multiply the result by the number of first-shape fingers in each subgroup plus one.

Abstract: A BGA (Ball Grid Array) package is proposed, which is characterized by the provision of an interdigitated power/ground ring layout scheme. By this layout scheme, the power ring and the ground ring are each formed with a line portion and a plurality of toothed portions; with the toothed portions of the power ring being are interdigitated with the toothed portions of the ground ring. Moreover, the power/ground vias are all connected to the toothed portions of the power ring and the ground ring, thereby leaving the line portions of the power ring and the ground ring unoccupied by the power/ground vias, allowing the routability of power/ground wires to be higher than the prior art. Moreover, solder bask is formed in such a manner as to cover all the toothed portions of the ground ring, so that power wires can be prevented from being short-circuited to the ground ring due to sagging.

Abstract: A BGA (Ball Grid Array) package is proposed, which is characterized by the provision of an interdigitated power/ground ring layout scheme. By this layout scheme, the power ring and the ground ring are each formed with a line portion and a plurality of toothed portions; with the toothed portions of the power ring being are interdigitated with the toothed portions of the ground ring. Moreover, the power/ground vias are all connected to the toothed portions of the power ring and the ground ring, thereby leaving the line portions of the power ring and the ground ring unoccupied by the power/ground vias, allowing the routability of power/ground wires to be higher than the prior art. Moreover, solder mask is formed in such a manner as to cover all the toothed portions of the ground ring, so that power wires can be prevented from being short-circuited to the ground ring due to sagging.

Abstract: An integrated-circuit package with a quick-to-count finger layout design on substrate is proposed, which can help fabrication engineers to visually check the total number of fingers on the substrate in a quick and accurate manner. The proposed integrated-circuit package is characterized by the provision of a line-up array of fingers which includes a plurality of first-shape fingers partitioned equally in number into a plurality of subgroups; and a plurality of second-shape fingers, which are substantially visually distinguishable in outer appearance from the first-shape fingers, and which are interposed between adjacent subgroups of the first-shape fingers to serve as count tokens. This finger layout design allows the fabrication engineers to visually check the total number of the line-up array of fingers on the substrate simply by counting through the second-shape fingers that serve as count tokens and then multiply the result by the number of first-shape fingers in each subgroup plus one.

Abstract: A method is proposed for the fabrication of plated circuit lines, including contact fingers, electrically-conductive traces, and solder-ball pads, over an BGA (Ball Grid Array) substrate. The method is characterized by that contact fingers, electrically-conductive traces, and solder-ball pads on the BGA substrate are interconnected with provisional bridging lines; and then, each integrally-connected group of the contact fingers, the electrically-conductive traces, and the solder-ball pads is connected via a branched plating line to a common plating bus. During plating process, the plating electrical current can be applied to the plating bus and then distributed over these branched plating lines to all of the contact fingers and the solder-ball pads. Finally, a drilling process is performed to break all the provisional bridging lines into open-circuited state.

Abstract: The present invention is a method for identifying defective elements in array molding of semiconductor packaging for mini BGA packaging substrate which comprises a circuit zone and a periphery zone. The method of the present invention is first to form a plurality of package sites disposed in array in the circuit zone, and to form a plurality of marks in a periphery zone. When a defective element is found in the package sites, a symbol is put at the mark or an electronic file is employed to record the location of the defective element, thereby, the defective element in the package sites of the molding array in the circuit zone can be identified.

Abstract: A multi-chip packaging substrate having a non-sticking test structure consists of a plurality of non-sticking test spots formed in the periphery zone outside the chip-packaging zone of a multi-chip packaging substrate. Each of these non-sticking test spots is electrically connected to an adjacent one of a plurality of chip pads respectively in the chip packaging zone through a plurality of conductive traces while there are no electrical connections connected one another among the chip pads.

Abstract: A semiconductor chip package is formed to be capable of reducing moisture erosion by configuring the bonding finger, the plating-conduction-line, and the trace on the chip carrier therein in such a way that the length of path for moisture to penetrate and to reach the bonding finger through a plating-conduction-line is significantly longer than those implemented in a conventional chip package.

Abstract: The present invention is a method for identifying defective elements in array molding of semiconductor packaging for mini BGA packaging substrate which comprises a circuit zone and a periphery zone. The method of the present invention is first to form a plurality of package sites disposed in array in the circuit zone, and to form a plurality of marks in a periphery zone. When a defective element is found in the package sites, a symbol is put at the mark or an electronic file is employed to record the location of the defective element, thereby, the defective element in the package sites of the molding array in the circuit zone can be identified.