Patents by Inventor Chih-Chuan Huang

Chih-Chuan Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11355045
    Abstract: A multiplexer circuit includes a first switch unit and a second switch unit. The first switch unit is electrically connected to a first data line and a first pixel circuit, and configured to turn on according to a first signal in a first time duration. The second switch unit is electrically connected to the first data line and a second pixel circuit, and configured to turn on according to a second signal in a second time duration. The first time duration and the second time duration substantially start or end at a same time, so that the first time duration and the second time duration have overlap.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: June 7, 2022
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Rong-Fu Lin, Chi Yu, Chih-Fu Yang, Jie-Chuan Huang, Sung-Yu Su
  • Patent number: 10984701
    Abstract: A source driver includes a phase generator, a control circuit, and an output circuit. The phase generator is configured to generate a plurality of output clock signals according to an input clock signal, in which the phases of the output clock signals are different from each other. The control circuit is configured to sequentially generate a plurality of control signals according to the output clock signals and a latch signal. The output circuit is configured to sequentially output a plurality of data voltages separately according to the control signals.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: April 20, 2021
    Assignee: Raydium Semiconductor Corporation
    Inventors: Chih-Chuan Huang, Yu-Chun Lin, Ching Chuan Chiu
  • Patent number: 10817044
    Abstract: A power saving control apparatus applied to a display driving circuit is disclosed. The power saving control apparatus includes a data analysis unit, a bias control unit and a charge sharing unit. The bias control unit is used to perform bias control. The charge sharing unit is used for charge sharing. The data analysis unit is coupled to the bias control unit and the charge sharing unit respectively. The data analysis unit instantly analyzes the display data to generate an instant analysis result and dynamically adjust the setting of bias and slew rate of the bias control unit according to the instant analysis result. The data analysis unit can dynamically adjust the setting of charge sharing range and charge sharing group number needed to be performed by the charge sharing unit according to the instant analysis result.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: October 27, 2020
    Assignee: Raydium Semiconductor Corporation
    Inventors: Chien-Hao Chen, Chih-Hao Wu, Chih-Chuan Huang, Sung-Bo Chen
  • Patent number: 10818211
    Abstract: A display apparatus is disclosed. The display apparatus includes a display panel, a master timing controller embedded driver (TED), N slave TEDs and an inter-chip bus. N is a positive integer. The display panel has (N+1) display areas. The master TED is disposed corresponding to a first display area. The N slave TEDs are disposed corresponding to a second display area˜a (N+1)-th display area respectively and controlled by the master TED. The inter-chip bus includes a first wire and a second wire coupled between the master TED and N slave TEDs respectively and used for bi-directionally transmitting clock signal and data signal respectively.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: October 27, 2020
    Assignee: Raydium Semiconductor Corporation
    Inventors: Shang-Han Yu, Sung-Bo Chen, Chih-Chuan Huang
  • Patent number: 10726805
    Abstract: A display driving apparatus applied to a panel is disclosed. The panel displays a first image with a first refresh rate. A first refresh cycle corresponding to the first refresh rate includes a refresh period and at least one non-refresh period. The display driving apparatus includes a real-time determination module and a data processing module. The real-time determination module is coupled to the panel and used to immediately determine whether the panel wants to replace the originally displayed first image with a second image during the first refresh cycle. The data processing module is coupled to the real-time determination module and the panel. If a determination result of the real-time determination module is yes, the data processing module immediately controls the panel to start to display the second image at a first time during the first refresh cycle.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: July 28, 2020
    Assignee: Raydium Semiconductor Corporation
    Inventors: Chih Chuan Huang, Yu-Yuan Chang, Wen-Fa Hsu
  • Publication number: 20200043433
    Abstract: A source driver with data dependent shared buffer design including a first data judging unit, a first buffer, a second buffer and a first output switch unit is disclosed. The first data judging unit judges whether a first input data and a second input data having a first polarization are the same. The first buffer and second buffer, coupled to the first data judging unit, are used to temporarily store the first input data and second input data respectively. The output switch unit is coupled to the first data judging unit, an output terminal of first buffer and an output terminal of second buffer respectively. When a judging result of first data judging unit is YES, the first data judging unit turns off the first buffer or second buffer and conducts the first output switch unit, so that the output terminals of first buffer and second buffer are coupled.
    Type: Application
    Filed: July 24, 2019
    Publication date: February 6, 2020
    Inventors: MING-HENG TSAI, CHIH-HSIEH JEN, CHIH-CHUAN HUANG
  • Publication number: 20200013328
    Abstract: A source driver includes a phase generator, a control circuit, and an output circuit. The phase generator is configured to generate a plurality of output clock signals according to an input clock signal, in which the phases of the output clock signals are different from each other. The control circuit is configured to sequentially generate a plurality of control signals according to the output clock signals and a latch signal. The output circuit is configured to sequentially output a plurality of data voltages separately according to the control signals.
    Type: Application
    Filed: June 20, 2019
    Publication date: January 9, 2020
    Inventors: CHIH-CHUAN HUANG, YU-CHUN LIN, CHING CHUAN CHIU
  • Publication number: 20200005697
    Abstract: A display apparatus is disclosed. The display apparatus includes a display panel, a master timing controller embedded driver (TED), N slave TEDs and an inter-chip bus. N is a positive integer. The display panel has (N+1) display areas. The master TED is disposed corresponding to a first display area. The N slave TEDs are disposed corresponding to a second display area˜a (N+1)-th display area respectively and controlled by the master TED. The inter-chip bus includes a first wire and a second wire coupled between the master TED and N slave TEDs respectively and used for bi-directionally transmitting clock signal and data signal respectively.
    Type: Application
    Filed: April 25, 2019
    Publication date: January 2, 2020
    Inventors: SHANG-HAN YU, SUNG-BO CHEN, CHIH-CHUAN HUANG
  • Publication number: 20190363728
    Abstract: A digital to analog converter circuit applied to a source driving apparatus is disclosed. The digital to analog converter circuit includes P-type transistors coupled in series, N-type transistors coupled in series and a substrate voltage control unit. The substrate voltage control unit is coupled to substrates of the P-type transistors and substrates of the N-type transistors respectively and used for controlling the substrates of the P-type transistors to have a first substrate voltage and controlling the substrates of the N-type transistors to have a second substrate voltage. The first substrate voltage is an operating voltage substituted by a specific voltage difference and the second substrate voltage is a ground voltage added by the specific voltage difference, and the operating voltage is higher than the ground voltage.
    Type: Application
    Filed: March 20, 2019
    Publication date: November 28, 2019
    Inventors: WAI-CHU WANG, CHIH-CHUAN HUANG
  • Publication number: 20190302873
    Abstract: A power saving control apparatus applied to a display driving circuit is disclosed. The power saving control apparatus includes a data analysis unit, a bias control unit and a charge sharing unit. The bias control unit is used to perform bias control. The charge sharing unit is used for charge sharing. The data analysis unit is coupled to the bias control unit and the charge sharing unit respectively. The data analysis unit instantly analyzes the display data to generate an instant analysis result and dynamically adjust the setting of bias and slew rate of the bias control unit according to the instant analysis result. The data analysis unit can dynamically adjust the setting of charge sharing range and charge sharing group number needed to be performed by the charge sharing unit according to the instant analysis result.
    Type: Application
    Filed: March 21, 2019
    Publication date: October 3, 2019
    Inventors: Chien-Hao CHEN, Chih-Hao WU, Chih-Chuan HUANG, Sung-Bo CHEN
  • Patent number: 10410596
    Abstract: A gate driving circuit including an input terminal, N delay units, a control signal bus, N buffer units and N output pads is disclosed. The input terminal receives a timing control signal including a total delay time. The N delay units are connected to the input terminal in order. Delay times of N delay units are adjustable and a sum of them is the total delay time. The control signal bus determines delay times of N delay units respectively according to the timing control signal. A first buffer unit of N buffer units is coupled between the input terminal and a first delay unit of N delay units; a second buffer unit, a third buffer unit . . . and an N-th buffer unit are coupled between two corresponding delay units respectively. The N output pads, correspondingly coupled to the N buffer units, output N gate driving signals respectively.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: September 10, 2019
    Assignee: Raydium Semiconductor Corporation
    Inventors: Yao Tsung Chang, Chih Chuan Huang
  • Patent number: 10380962
    Abstract: A driving circuit applied to a LCD apparatus includes N driver chips, a signal source, a WOA wire, a COF wire. Each driver chip is COF-packaged and correspondingly coupled to L output channels. N and L are positive integers and N?2. The signal source is coupled to L output channels of the first driver chip. One terminal of WOA wire is coupled to L output channels of the second driver chip. One terminal of the COF wire is coupled between the signal source and a first output channel of the first driver chip and another terminal of the COF wire is coupled to another terminal of WOA wire. The resistance of COF wire is far smaller than a first internal resistance between the first output channel and L-th output channel of first driver chip and the resistance of WOA wire is substantially equal to first internal resistance.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: August 13, 2019
    Assignee: Raydium Semiconductor Corporation
    Inventors: E-Ling Huang, Chih Chuan Huang, Wen-Tsung Lin
  • Publication number: 20190087261
    Abstract: An error detection circuit, applied to a digital communication system with embedded clock, includes a time delay unit, a clock embedding encoding unit, a comparing unit and a packet error counting unit. The time delay unit delays a first digital encoded signal for a period of time. The clock embedding encoding unit generates a second digital encoded signal according to a first digital decoded signal, wherein the first digital decoded signal is generated by decoding the first digital encoded signal. The comparing unit is coupled to the time delay unit and the clock embedding encoding unit respectively and compares the first digital encoded signal with the second digital encoded signal to generate a compared result. The packet error counting unit is coupled to the comparing unit and counts a packet error rate according to the compared result and then provides a flag according to the packet error rate.
    Type: Application
    Filed: September 21, 2018
    Publication date: March 21, 2019
    Inventors: CHIH-CHUAN HUANG, SUNG-BO CHEN, YUE-TING WU
  • Publication number: 20190073979
    Abstract: A display driving apparatus applied to a panel is disclosed. The panel displays a first image with a first refresh rate. A first refresh cycle corresponding to the first refresh rate includes a refresh period and at least one non-refresh period. The display driving apparatus includes a real-time determination module and a data processing module. The real-time determination module is coupled to the panel and used to immediately determine whether the panel wants to replace the originally displayed first image with a second image during the first refresh cycle. The data processing module is coupled to the real-time determination module and the panel. If a determination result of the real-time determination module is yes, the data processing module immediately controls the panel to start to display the second image at a first time during the first refresh cycle.
    Type: Application
    Filed: August 31, 2018
    Publication date: March 7, 2019
    Inventors: CHIH CHUAN HUANG, YU-YUAN CHANG, WEN-FA HSU
  • Patent number: 10109229
    Abstract: The present invention provides a display panel driving circuit and compensation method thereof. The display panel driving circuit comprises a near end load, a far end load, an operating circuit and a pre-charging control circuit. The operating circuit is configured to receive display data. The pre-charging control circuit is coupled to the near end load and the far end load respectively. The pre-charging control circuit outputs a first signal and a second signal to the near end load and the far end load respectively according to the display data that a first waveform from the near end load is the same as a second waveform from the far end load.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: October 23, 2018
    Assignee: Raydium Semiconductor Corporation
    Inventors: Shun-Yuan Wang, Chih-Hsien Jen, Chih-Chuan Huang, Wen-Tsung Lin
  • Patent number: 9978324
    Abstract: A driver applied to a display apparatus is disclosed. The driver includes 2(N+1) source channels, M display lines, and an output polarity control module. N and M are positive integers. Polarity outputs of the M display lines are independently controlled and have no dependencies between each other. The output polarity control module provides (N+1) polarity inversion control signals. A K-th polarity inversion control signal of the (N+1) polarity inversion control signals controls polarities outputted by the (2K?1)-th source channel and the 2K-th source channel of the 2(N+1) source channels. K is a positive integer and 1?K?(N+1).
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: May 22, 2018
    Assignee: Raydium Semiconductor Corporation
    Inventors: Kun-Chan Hsieh, Chih Chuan Huang, Feng-Li Lin
  • Publication number: 20180040267
    Abstract: A display apparatus and a driving circuit thereof are disclosed. The display apparatus includes a display panel, a timing controller and a plurality of driving circuits. The timing controller is used to generate a plurality of independent timing control signals respectively. The plurality of driving circuits is coupled between the timing controller and the display panel respectively. The plurality of driving circuits receives the plurality of independent timing control signals respectively and generates a plurality of independent clock signals respectively. The plurality of driving circuits randomly performs different modulations on the plurality of independent clock signals respectively to make different changes on phases of the plurality of clock signals with time. Therefore, the phases of the plurality of clock signals generated by the plurality of driving circuits will be different.
    Type: Application
    Filed: August 2, 2017
    Publication date: February 8, 2018
    Inventors: Chih Chuan HUANG, Zhen-Yu LI
  • Publication number: 20170287426
    Abstract: A gate driving circuit including an input terminal, N delay units, a control signal bus, N buffer units and N output pads is disclosed. The input terminal receives a timing control signal including a total delay time. The N delay units are connected to the input terminal in order. Delay times of N delay units are adjustable and a sum of them is the total delay time. The control signal bus determines delay times of N delay units respectively according to the timing control signal. A first buffer unit of N buffer units is coupled between the input terminal and a first delay unit of N delay units; a second buffer unit, a third buffer unit . . . and an N-th buffer unit are coupled between two corresponding delay units respectively. The N output pads, correspondingly coupled to the N buffer units, output N gate driving signals respectively.
    Type: Application
    Filed: March 29, 2017
    Publication date: October 5, 2017
    Inventors: YAO TSUNG CHANG, CHIH CHUAN HUANG
  • Patent number: 9705455
    Abstract: A random chopper control circuit is disclosed. The random chopper control circuit is coupled to an operational amplifier. The random chopper control circuit includes a random generator. The random generator is configured to generate a random chopper control signal and output the random chopper control signal to the operational amplifier to control an operation of the operational amplifier.
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: July 11, 2017
    Assignee: Raydium Semiconductor Corporation
    Inventors: Chih-Chuan Huang, Wen-Tsung Lin
  • Publication number: 20170154599
    Abstract: A display device of the present invention includes a display substrate and a source driver. The display substrate includes a display area and a peripheral area surrounding the display area. At least a fan-out portion is formed on the peripheral area and distributes along a first direction. The fan-out portion has a plurality of fan-out wires. The source driver is connected to one side of the fan-out portion opposite to the display area. The source driver includes a plurality of driving circuits. An output end of each driving circuit has a modulation unit coupled to one of the plurality of the fan-out wires. The fan-out portion has a resistance value distribution along the first direction. The resistance value of the modulation unit in each driving circuit is modulated according to the resistance value distribution.
    Type: Application
    Filed: November 30, 2016
    Publication date: June 1, 2017
    Inventors: Chih-Chuan HUANG, Shun-Yuan WANG