Abstract: A semiconductor device structure includes a source/drain feature comprising a first surface, a second surface opposing the first surface, and a sidewall connecting the first surface to the second surface. The structure also includes a dielectric layer having a continuous surface in contact with the entire second surface of the source/drain feature, a semiconductor layer having a first surface, a second surface opposing the first surface, and a sidewall connecting the first surface to the second surface, wherein the sidewall of the semiconductor layer is in contact with the sidewall of the source/drain feature. The structure also includes a gate dielectric layer in contact with the continuous surface of the dielectric layer and the second surface of the semiconductor layer, and a gate electrode layer surrounding a portion of the semiconductor layer.

Abstract: Disclosed is a thermal conduction-electrical conduction isolated circuit board with a ceramic substrate and a power transistor embedded, mainly comprising: a dielectric material layer, a heat-dissipating ceramic block, a securing portion, a stepped metal electrode layer, a power transistor, and a dielectric material packaging, wherein a via hole is formed in the dielectric material layer, the heat-dissipating ceramic block is correspondingly embedded in the via hole, the heat-dissipating ceramic block has a thermal conductivity higher than that of the dielectric material layer and a thickness less than that of the dielectric material layer, the stepped metal electrode layer conducts electricity and heat for the power transistor, the dielectric material packaging is configured to partially expose the source connecting pin, drain connecting pin, and gate connecting pin of the encapsulated stepped metal electrode layer.

Abstract: A method of fabricating a device includes providing a fin element in a device region and forming a dummy gate over the fin element. In some embodiments, the method further includes forming a source/drain feature within a source/drain region adjacent to the dummy gate. In some cases, the source/drain feature includes a bottom region and a top region contacting the bottom region at an interface interposing the top and bottom regions. In some embodiments, the method further includes performing a plurality of dopant implants into the source/drain feature. In some examples, the plurality of dopant implants includes implantation of a first dopant within the bottom region and implantation of a second dopant within the top region. In some embodiments, the first dopant has a first graded doping profile within the bottom region, and the second dopant has a second graded doping profile within the top region.

Abstract: An antiferroelectric field effect transistor (Anti-FeFET) of a memory cell includes an antiferroelectric layer instead of a ferroelectric layer. The antiferroelectric layer may operate based on a programmed state and an erased state in which the antiferroelectric layer is in a fully polarized alignment and a non-polarized alignment (or a random state of polarization), respectively. This enables the antiferroelectric layer in the FeFET to provide a sharper/larger voltage drop for an erase operation of the FeFET (e.g., in which the FeFET switches or transitions from the programmed state to the erased state) relative to a ferroelectric material layer that operates based on switching between two opposing fully polarized states.

Abstract: The present invention discloses an integrated choke assembly comprising: a base having a main body structure, a first protruding part and a second protruding part. A first choke has a first magnetic core and a first winding, wherein the first protruding part is arranged through the first opening of the first magnetic core so that the first choke is arranged on the upper surface of the main body structure, and the first winding is wound on the first magnetic core. A second choke has a second magnetic core and a second winding, wherein the second protruding part is arranged through the second opening of the second magnetic core so that the second choke is arranged on the lower surface of the main body structure, and the second winding is wound on the second magnetic core.

Abstract: An enhancement mode high electron mobility transistor (HEMT) includes a group III-V semiconductor body, a group III-V barrier layer and a gate structure. The group III-V barrier layer is disposed on the group III-V semiconductor body, and the gate structure is a stacked structure disposed on the group III-V barrier layer. The gate structure includes a gate dielectric and a group III-V gate layer disposed on the gate dielectric, and the thickness of the gate dielectric is between 15 nm to 25 nm.

Abstract: A source driver includes a phase generator, a control circuit, and an output circuit. The phase generator is configured to generate a plurality of output clock signals according to an input clock signal, in which the phases of the output clock signals are different from each other. The control circuit is configured to sequentially generate a plurality of control signals according to the output clock signals and a latch signal. The output circuit is configured to sequentially output a plurality of data voltages separately according to the control signals.

Abstract: A display apparatus is disclosed. The display apparatus includes a display panel, a master timing controller embedded driver (TED), N slave TEDs and an inter-chip bus. N is a positive integer. The display panel has (N+1) display areas. The master TED is disposed corresponding to a first display area. The N slave TEDs are disposed corresponding to a second display area˜a (N+1)-th display area respectively and controlled by the master TED. The inter-chip bus includes a first wire and a second wire coupled between the master TED and N slave TEDs respectively and used for bi-directionally transmitting clock signal and data signal respectively.

Abstract: A power saving control apparatus applied to a display driving circuit is disclosed. The power saving control apparatus includes a data analysis unit, a bias control unit and a charge sharing unit. The bias control unit is used to perform bias control. The charge sharing unit is used for charge sharing. The data analysis unit is coupled to the bias control unit and the charge sharing unit respectively. The data analysis unit instantly analyzes the display data to generate an instant analysis result and dynamically adjust the setting of bias and slew rate of the bias control unit according to the instant analysis result. The data analysis unit can dynamically adjust the setting of charge sharing range and charge sharing group number needed to be performed by the charge sharing unit according to the instant analysis result.

Abstract: A display driving apparatus applied to a panel is disclosed. The panel displays a first image with a first refresh rate. A first refresh cycle corresponding to the first refresh rate includes a refresh period and at least one non-refresh period. The display driving apparatus includes a real-time determination module and a data processing module. The real-time determination module is coupled to the panel and used to immediately determine whether the panel wants to replace the originally displayed first image with a second image during the first refresh cycle. The data processing module is coupled to the real-time determination module and the panel. If a determination result of the real-time determination module is yes, the data processing module immediately controls the panel to start to display the second image at a first time during the first refresh cycle.

Abstract: A source driver with data dependent shared buffer design including a first data judging unit, a first buffer, a second buffer and a first output switch unit is disclosed. The first data judging unit judges whether a first input data and a second input data having a first polarization are the same. The first buffer and second buffer, coupled to the first data judging unit, are used to temporarily store the first input data and second input data respectively. The output switch unit is coupled to the first data judging unit, an output terminal of first buffer and an output terminal of second buffer respectively. When a judging result of first data judging unit is YES, the first data judging unit turns off the first buffer or second buffer and conducts the first output switch unit, so that the output terminals of first buffer and second buffer are coupled.

Abstract: A source driver includes a phase generator, a control circuit, and an output circuit. The phase generator is configured to generate a plurality of output clock signals according to an input clock signal, in which the phases of the output clock signals are different from each other. The control circuit is configured to sequentially generate a plurality of control signals according to the output clock signals and a latch signal. The output circuit is configured to sequentially output a plurality of data voltages separately according to the control signals.

Abstract: A display apparatus is disclosed. The display apparatus includes a display panel, a master timing controller embedded driver (TED), N slave TEDs and an inter-chip bus. N is a positive integer. The display panel has (N+1) display areas. The master TED is disposed corresponding to a first display area. The N slave TEDs are disposed corresponding to a second display area˜a (N+1)-th display area respectively and controlled by the master TED. The inter-chip bus includes a first wire and a second wire coupled between the master TED and N slave TEDs respectively and used for bi-directionally transmitting clock signal and data signal respectively.

Abstract: A digital to analog converter circuit applied to a source driving apparatus is disclosed. The digital to analog converter circuit includes P-type transistors coupled in series, N-type transistors coupled in series and a substrate voltage control unit. The substrate voltage control unit is coupled to substrates of the P-type transistors and substrates of the N-type transistors respectively and used for controlling the substrates of the P-type transistors to have a first substrate voltage and controlling the substrates of the N-type transistors to have a second substrate voltage. The first substrate voltage is an operating voltage substituted by a specific voltage difference and the second substrate voltage is a ground voltage added by the specific voltage difference, and the operating voltage is higher than the ground voltage.

Abstract: A power saving control apparatus applied to a display driving circuit is disclosed. The power saving control apparatus includes a data analysis unit, a bias control unit and a charge sharing unit. The bias control unit is used to perform bias control. The charge sharing unit is used for charge sharing. The data analysis unit is coupled to the bias control unit and the charge sharing unit respectively. The data analysis unit instantly analyzes the display data to generate an instant analysis result and dynamically adjust the setting of bias and slew rate of the bias control unit according to the instant analysis result. The data analysis unit can dynamically adjust the setting of charge sharing range and charge sharing group number needed to be performed by the charge sharing unit according to the instant analysis result.

Abstract: A gate driving circuit including an input terminal, N delay units, a control signal bus, N buffer units and N output pads is disclosed. The input terminal receives a timing control signal including a total delay time. The N delay units are connected to the input terminal in order. Delay times of N delay units are adjustable and a sum of them is the total delay time. The control signal bus determines delay times of N delay units respectively according to the timing control signal. A first buffer unit of N buffer units is coupled between the input terminal and a first delay unit of N delay units; a second buffer unit, a third buffer unit . . . and an N-th buffer unit are coupled between two corresponding delay units respectively. The N output pads, correspondingly coupled to the N buffer units, output N gate driving signals respectively.

Abstract: A driving circuit applied to a LCD apparatus includes N driver chips, a signal source, a WOA wire, a COF wire. Each driver chip is COF-packaged and correspondingly coupled to L output channels. N and L are positive integers and N?2. The signal source is coupled to L output channels of the first driver chip. One terminal of WOA wire is coupled to L output channels of the second driver chip. One terminal of the COF wire is coupled between the signal source and a first output channel of the first driver chip and another terminal of the COF wire is coupled to another terminal of WOA wire. The resistance of COF wire is far smaller than a first internal resistance between the first output channel and L-th output channel of first driver chip and the resistance of WOA wire is substantially equal to first internal resistance.

Abstract: An error detection circuit, applied to a digital communication system with embedded clock, includes a time delay unit, a clock embedding encoding unit, a comparing unit and a packet error counting unit. The time delay unit delays a first digital encoded signal for a period of time. The clock embedding encoding unit generates a second digital encoded signal according to a first digital decoded signal, wherein the first digital decoded signal is generated by decoding the first digital encoded signal. The comparing unit is coupled to the time delay unit and the clock embedding encoding unit respectively and compares the first digital encoded signal with the second digital encoded signal to generate a compared result. The packet error counting unit is coupled to the comparing unit and counts a packet error rate according to the compared result and then provides a flag according to the packet error rate.

Abstract: A display driving apparatus applied to a panel is disclosed. The panel displays a first image with a first refresh rate. A first refresh cycle corresponding to the first refresh rate includes a refresh period and at least one non-refresh period. The display driving apparatus includes a real-time determination module and a data processing module. The real-time determination module is coupled to the panel and used to immediately determine whether the panel wants to replace the originally displayed first image with a second image during the first refresh cycle. The data processing module is coupled to the real-time determination module and the panel. If a determination result of the real-time determination module is yes, the data processing module immediately controls the panel to start to display the second image at a first time during the first refresh cycle.

Abstract: The present invention provides a display panel driving circuit and compensation method thereof. The display panel driving circuit comprises a near end load, a far end load, an operating circuit and a pre-charging control circuit. The operating circuit is configured to receive display data. The pre-charging control circuit is coupled to the near end load and the far end load respectively. The pre-charging control circuit outputs a first signal and a second signal to the near end load and the far end load respectively according to the display data that a first waveform from the near end load is the same as a second waveform from the far end load.