Abstract: A driver applied to a display apparatus is disclosed. The driver includes 2(N+1) source channels, M display lines, and an output polarity control module. N and M are positive integers. Polarity outputs of the M display lines are independently controlled and have no dependencies between each other. The output polarity control module provides (N+1) polarity inversion control signals. A K-th polarity inversion control signal of the (N+1) polarity inversion control signals controls polarities outputted by the (2K?1)-th source channel and the 2K-th source channel of the 2(N+1) source channels. K is a positive integer and 1?K?(N+1).

Abstract: A display apparatus and a driving circuit thereof are disclosed. The display apparatus includes a display panel, a timing controller and a plurality of driving circuits. The timing controller is used to generate a plurality of independent timing control signals respectively. The plurality of driving circuits is coupled between the timing controller and the display panel respectively. The plurality of driving circuits receives the plurality of independent timing control signals respectively and generates a plurality of independent clock signals respectively. The plurality of driving circuits randomly performs different modulations on the plurality of independent clock signals respectively to make different changes on phases of the plurality of clock signals with time. Therefore, the phases of the plurality of clock signals generated by the plurality of driving circuits will be different.

Abstract: A gate driving circuit including an input terminal, N delay units, a control signal bus, N buffer units and N output pads is disclosed. The input terminal receives a timing control signal including a total delay time. The N delay units are connected to the input terminal in order. Delay times of N delay units are adjustable and a sum of them is the total delay time. The control signal bus determines delay times of N delay units respectively according to the timing control signal. A first buffer unit of N buffer units is coupled between the input terminal and a first delay unit of N delay units; a second buffer unit, a third buffer unit . . . and an N-th buffer unit are coupled between two corresponding delay units respectively. The N output pads, correspondingly coupled to the N buffer units, output N gate driving signals respectively.

Abstract: A random chopper control circuit is disclosed. The random chopper control circuit is coupled to an operational amplifier. The random chopper control circuit includes a random generator. The random generator is configured to generate a random chopper control signal and output the random chopper control signal to the operational amplifier to control an operation of the operational amplifier.

Abstract: A display device of the present invention includes a display substrate and a source driver. The display substrate includes a display area and a peripheral area surrounding the display area. At least a fan-out portion is formed on the peripheral area and distributes along a first direction. The fan-out portion has a plurality of fan-out wires. The source driver is connected to one side of the fan-out portion opposite to the display area. The source driver includes a plurality of driving circuits. An output end of each driving circuit has a modulation unit coupled to one of the plurality of the fan-out wires. The fan-out portion has a resistance value distribution along the first direction. The resistance value of the modulation unit in each driving circuit is modulated according to the resistance value distribution.

Abstract: The present invention provides a display panel driving circuit and compensation method thereof. The display panel driving circuit comprises a near end load, a far end load, an operating circuit and a pre-charging control circuit. The operating circuit is configured to receive display data. The pre-charging control circuit is coupled to the near end load and the far end load respectively. The pre-charging control circuit outputs a first signal and a second signal to the near end load and the far end load respectively according to the display data that a first waveform from the near end load is the same as a second waveform from the far end load.

Abstract: A driving circuit applied to a LCD apparatus includes N driver chips, a signal source, a WOA wire, a COF wire. Each driver chip is COF-packaged and correspondingly coupled to L output channels. N and L are positive integers and N?2. The signal source is coupled to L output channels of the first driver chip. One terminal of WOA wire is coupled to L output channels of the second driver chip. One terminal of the COF wire is coupled between the signal source and a first output channel of the first driver chip and another terminal of the COF wire is coupled to another terminal of WOA wire. The resistance of COF wire is far smaller than a first internal resistance between the first output channel and L-th output channel of first driver chip and the resistance of WOA wire is substantially equal to first internal resistance.

Abstract: A driver applied to a display apparatus is disclosed. The driver includes 2(N+1) source channels, M display lines, and an output polarity control module. N and M are positive integers. Polarity outputs of the M display lines are independently controlled and have no dependencies between each other. The output polarity control module provides (N+1) polarity inversion control signals. A K-th polarity inversion control signal of the (N+1) polarity inversion control signals controls polarities outputted by the (2K?1)-th source channel and the 2K-th source channel of the 2(N+1) source channels. K is a positive integer and 1?K?(N+1).

Abstract: A driving circuit includes at least one reference voltage source, at least one offset unit, and at least one buffer module. The at least one reference voltage source generates a reference voltage. The at least one offset unit generates an offset voltage, wherein the offset voltage and the reference voltage form a judging voltage range. The at least one buffer module has a first input end, a second input end, and an output end, wherein the first input end receives an analog voltage; the at least one reference voltage source is connected with the second input end; the at least one buffer module, according as whether the analog voltage is within the judging voltage range, outputs a pass logic signal or a fail logic signal at the output end. Particularly, the buffer module has Built-In-Self-Test (BIST) function and can increase test efficiency and voltage accuracy.

Abstract: A driving circuit for connecting a display module is provided. The driving circuit includes a polarity control module, an output control module, and a detecting module. The polarity control module provides a polarity control signal. The output control module is connected with the polarity control module and provides a plurality of output control signals. The detecting module is coupled with the polarity control module and the output control module, wherein the detecting module detects the polarity control signal and selectively controls the output control module to operate in at least one of a first control mode and a second control mode to control the output control signals.

Abstract: A random chopper control circuit is disclosed. The random chopper control circuit is coupled to an operational amplifier. The random chopper control circuit includes a random generator. The random generator is configured to generate a random chopper control signal and output the random chopper control signal to the operational amplifier to control an operation of the operational amplifier.

Abstract: A driving apparatus applied in a liquid crystal display is disclosed. The driving apparatus at least includes a first latch, a second latch, an output buffer, and a slew rate enhancing module. The first latch is used to store a second data signal. The second latch is used to store a first data signal. The first data signal is previous to the second data signal. The slew rate enhancing module is used to compare the first data signal and the second data signal to generate a compared result, and correspondingly output a control signal to the output buffer according to the compared result to control a driving current of the output buffer.

Abstract: A driving circuit includes at least one reference voltage source, at least one offset unit, and at least one buffer module. The at least one reference voltage source generates a reference voltage. The at least one offset unit generates an offset voltage, wherein the offset voltage and the reference voltage form a judging voltage range. The at least one buffer module has a first input end, a second input end, and an output end, wherein the first input end receives an analog voltage; the at least one reference voltage source is connected with the second input end; the at least one buffer module, according as whether the analog voltage is within the judging voltage range, outputs a pass logic signal or a fail logic signal at the output end. Particularly, the buffer module has Built-In-Self-Test (BIST) function and can increase test efficiency and voltage accuracy.

Abstract: A driving circuit for connecting a display module is provided. The driving circuit includes a polarity control module, an output control module, and a detecting module. The polarity control module provides a polarity control signal. The output control module is connected with the polarity control module and provides a plurality of output control signals. The detecting module is coupled with the polarity control module and the output control module, wherein the detecting module detects the polarity control signal and selectively controls the output control module to operate in at least one of a first control mode and a second control mode to control the output control signals.

Abstract: A driving apparatus applied in a liquid crystal display is disclosed. The driving apparatus at least includes a first latch, a second latch, an output buffer, and a slew rate enhancing module. The first latch is used to store a second data signal. The second latch is used to store a first data signal. The first data signal is previous to the second data signal. The slew rate enhancing module is used to compare the first data signal and the second data signal to generate a compared result, and correspondingly output a control signal to the output buffer according to the compared result to control a driving current of the output buffer.

Abstract: The invention discloses a controlling apparatus for a signal outputting circuit in an electronic system. The controlling apparatus includes a detecting circuit, a switch, and a controlling circuit. The detecting circuit is used for detecting whether the electronic system has an abnormal condition. The switch is electrically connected between a signal receiving terminal and the signal outputting circuit. The controlling circuit is electrically connected between the detecting circuit and the switch. Once the detecting circuit detects that the electronic system has the abnormal condition, the controlling circuit sets the switch into a high-impedance state.

Abstract: A driving circuit applied in an electronic display apparatus is provided. The driving circuit includes a first exchange circuit and a first buffer. The first buffer includes first and second input stages, a second exchange circuit and first and second output stages. The first exchange circuit selectively couples a first input signal and a first output signal outputted from the first output stage to one of the first and the second input stages; and selectively couples a second input signal and a second output signal outputted from the second output stage to the other of the first and the second input stages. The second exchange circuit selectively couples the first input stage to one of the first and the second output stages and selectively couples the second input stage to the other of the first and the second output stages.

Abstract: The invention discloses a controlling apparatus for a signal outputting circuit in an electronic system. The controlling apparatus includes a detecting circuit, a switch, and a controlling circuit. The detecting circuit is used for detecting whether the electronic system has an abnormal condition. The switch is electrically connected between a signal receiving terminal and the signal outputting circuit. The controlling circuit is electrically connected between the detecting circuit and the switch. Once the detecting circuit detects that the electronic system has the abnormal condition, the controlling circuit sets the switch into a high-impedance state.

Abstract: A segmented transmission signal circuit is provided with a parallel bus of data transmission. The bus includes a plurality of sections, each section transmits a corresponding parallel data of multiple bits, and the parallel data corresponding to different sections are in different bit orders.

Abstract: The invention discloses a controlling apparatus for a signal outputting circuit in an electronic system. The controlling apparatus includes a detecting circuit, a switch, and a controlling circuit. The detecting circuit is used for detecting whether the electronic system has an abnormal condition. The switch is electrically connected between a signal receiving terminal and the signal outputting circuit. The controlling circuit is electrically connected between the detecting circuit and the switch. Once the detecting circuit detects that the electronic system has the abnormal condition, the controlling circuit sets the switch into a high-impedance state.