Patents by Inventor Chih-Chung Chiu
Chih-Chung Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240096705Abstract: A semiconductor device includes a plurality of channel layers vertically separated from one another. The semiconductor device also includes an active gate structure comprising a lower portion and an upper portion. The lower portion wraps around each of the plurality of channel layers. The semiconductor device further includes a gate spacer extending along a sidewall of the upper portion of the active gate structure. The gate spacer has a bottom surface. Moreover, a dummy gate dielectric layer is disposed between the gate spacer and a topmost channel layer of plurality of channel layers. The dummy gate dielectric layer is in contact with a top surface of the topmost channel layer, the bottom surface of the gate spacer, and the sidewall of the gate structure.Type: ApplicationFiled: November 30, 2023Publication date: March 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuei-Yu Kao, Chen-Yui Yang, Hsien-Chung Huang, Chao-Cheng Chen, Shih-Yao Lin, Chih-Chung Chiu, Chih-Han Lin, Chen-Ping Chen, Ke-Chia Tseng, Ming-Ching Chang
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Publication number: 20240080024Abstract: A driving method for a multiple frequency coupling generator is provided. The method includes: in normal operations, interpreting an input digital control signal transmitted from a digital signal processor into an interpreted digital control signal; interpreting the interpreted digital control signal into a plurality of magnetic coupling signals by a magnetic coupling switch circuit; performing signal recovery and differential delay on the magnetic coupling signals by an interlocking circuit for reducing time difference and signal loss of the magnetic coupling signals; and when the interlocking circuit determines that the magnetic coupling signals have substantially no time difference and no signal loss, transforming the magnetic coupling signals into a first driving signal and a second driving signal by a switch circuit, a driver circuit and an output pad group to drive a backend driving loop.Type: ApplicationFiled: March 30, 2023Publication date: March 7, 2024Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chih-Chung CHIU, Hung-Yi TENG, Chi-Chung LIAO, Shou-Chung HSIEH, Ke-Horng CHEN, Yan-Fu JHOU
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Patent number: 11908746Abstract: A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. The semiconductor device includes a gate structure that comprises a lower portion and an upper portion, wherein the lower portion wraps around each of the plurality of semiconductor layers. The semiconductor device includes a gate spacer that extends along a sidewall of the upper portion of the gate structure and has a bottom surface. A portion of the bottom surface of the gate spacer and a top surface of a topmost one of the plurality of semiconductor layers form an angle that is less than 90 degrees.Type: GrantFiled: August 28, 2021Date of Patent: February 20, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuei-Yu Kao, Chao-Cheng Chen, Chih-Han Lin, Chen-Ping Chen, Ming-Ching Chang, Shih-Yao Lin, Chih-Chung Chiu
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Publication number: 20240014293Abstract: Provided are devices with replacement structures and methods for fabricating such structures. A method includes forming a layer over a semiconductor material having a top surface in a horizontal plane; forming a dummy structure over the layer, wherein the dummy structure has sidewall, wherein the dummy structure lies directly over a first region of the layer and over a first region of the semiconductor material under the first region of the layer, and wherein the dummy structure does not lie directly over a second region of the layer or over a second region of the semiconductor material under the second region of the layer, and removing the second region of the layer and forming a side edge of the first region of the layer, wherein the side edge forms an angle of from 90 to 100 degrees with the horizontal plane.Type: ApplicationFiled: July 11, 2022Publication date: January 11, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuei-Yu Kao, Shih-Yao Lin, Chen-Ping Chen, Chih-Chung Chiu, Chih-Han Li, Ming-Ching Chang, Chao-Cheng Chen
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Patent number: 11842929Abstract: A semiconductor device includes a plurality of channel layers vertically separated from one another. The semiconductor device also includes an active gate structure comprising a lower portion and an upper portion. The lower portion wraps around each of the plurality of channel layers. The semiconductor device further includes a gate spacer extending along a sidewall of the upper portion of the active gate structure. The gate spacer has a bottom surface. Moreover, a dummy gate dielectric layer is disposed between the gate spacer and a topmost channel layer of plurality of channel layers. The dummy gate dielectric layer is in contact with a top surface of the topmost channel layer, the bottom surface of the gate spacer, and the sidewall of the gate structure.Type: GrantFiled: August 30, 2021Date of Patent: December 12, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuei-Yu Kao, Shih-Yao Lin, Chen-Ping Chen, Chih-Chung Chiu, Chen-Yui Yang, Ke-Chia Tseng, Hsien-Chung Huang, Chih-Han Lin, Ming-Ching Chang, Chao-Cheng Chen
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Publication number: 20230395677Abstract: A cyclic process including an etching process, a passivation process, and a pumping out process is provided to prevent over etching of the sacrificial gate electrode, particularly when near a high-k dielectric feature. The cyclic process solves the problems of failed gate electrode layer at an end of channel region and enlarges filling windows for replacement gate structures, thus improving channel control. Compared to state-of-art solutions, embodiments of the present disclosure also enlarge volume of source/drain regions, thus improving device performance.Type: ApplicationFiled: June 2, 2022Publication date: December 7, 2023Inventors: Kuei-Yu KAO, Shih-Yao LIN, Chen-Ping CHEN, Chih-Chung CHIU, Ke-Chia TSENG, Chih-Han LIN, Ming-Ching CHANG, Chao-Cheng CHEN
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Publication number: 20230326990Abstract: The disclosure is directed towards semiconductor devices and methods of manufacturing the semiconductor devices. The methods include forming fins in a device region and forming other fins in a multilayer stack of semiconductor materials in a multi-channel device region. A topmost nanostructure may be exposed in the multi-channel device region by removing a sacrificial layer from the top of the multilayer stack. Once removed, a stack of nanostructures are formed from the multilayer stack. A native oxide layer is formed to a first thickness over the topmost nanostructure and to a second thickness over the remaining nanostructures of the stack, the first thickness being greater than the second thickness. A gate dielectric is formed over the fins in the device region. A gate electrode is formed over the gate dielectric in the device region and surrounding the native oxide layer in the multi-channel device region.Type: ApplicationFiled: June 14, 2023Publication date: October 12, 2023Inventors: Shih-Yao Lin, Chih-Chung Chiu, Kuei-Yu Kao, Chen-Ping Chen, Chih-Han Lin
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Patent number: 11715779Abstract: The disclosure is directed towards semiconductor devices and methods of manufacturing the semiconductor devices. The methods include forming fins in a device region and forming other fins in a multilayer stack of semiconductor materials in a multi-channel device region. A topmost nanostructure may be exposed in the multi-channel device region by removing a sacrificial layer from the top of the multilayer stack. Once removed, a stack of nanostructures are formed from the multilayer stack. A native oxide layer is formed to a first thickness over the topmost nanostructure and to a second thickness over the remaining nanostructures of the stack, the first thickness being greater than the second thickness. A gate dielectric is formed over the fins in the device region. A gate electrode is formed over the gate dielectric in the device region and surrounding the native oxide layer in the multi-channel device region.Type: GrantFiled: February 28, 2022Date of Patent: August 1, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shih-Yao Lin, Chih-Chung Chiu, Kuei-Yu Kao, Chen-Ping Chen, Chih-Han Lin
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Patent number: 11602128Abstract: An ear tag module includes a rod member, a spike, a circuit component, and a temperature sensor. The spike is disposed on one side of the rod member, and the circuit component is disposed on another side of the rod member. The temperature sensor is electrically connected to the circuit component. When the spike penetrates an ear, the ear is in contact with a sensing area of the rod member, and the temperature sensor is located in the rod member to detect a temperature of the ear and transmit at least one temperature sensing information to the circuit component.Type: GrantFiled: May 27, 2020Date of Patent: March 14, 2023Assignee: Industrial Technology Research InstituteInventors: Shu-Jung Yang, Yu-Lin Chao, Chih-Chung Chiu, Heng-Chieh Chien
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Publication number: 20230060825Abstract: A semiconductor device includes a plurality of channel layers vertically separated from one another. The semiconductor device also includes an active gate structure comprising a lower portion and an upper portion. The lower portion wraps around each of the plurality of channel layers. The semiconductor device further includes a gate spacer extending along a sidewall of the upper portion of the active gate structure. The gate spacer has a bottom surface. Moreover, a dummy gate dielectric layer is disposed between the gate spacer and a topmost channel layer of plurality of channel layers. The dummy gate dielectric layer is in contact with a top surface of the topmost channel layer, the bottom surface of the gate spacer, and the sidewall of the gate structure.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuei-Yu Kao, Shih-Yao Lin, Chen-Ping Chen, Chih-Chung Chiu, Chen-Yui Yang, Ke-Chia Tseng, Hsien-Chung Huang, Chih-Han Lin, Ming-Ching Chang, Chao-Cheng Chen
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Publication number: 20230061815Abstract: A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. The semiconductor device includes a gate structure that comprises a lower portion and an upper portion, wherein the lower portion wraps around each of the plurality of semiconductor layers. The semiconductor device includes a gate spacer that extends along a sidewall of the upper portion of the gate structure and has a bottom surface. A portion of the bottom surface of the gate spacer and a top surface of a topmost one of the plurality of semiconductor layers form an angle that is less than 90 degrees.Type: ApplicationFiled: August 28, 2021Publication date: March 2, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuei-Yu Kao, Chao-Cheng Chen, Chih-Han Lin, Chen-Ping Chen, Ming-Ching Chang, Shih-Yao Lin, Chih-Chung Chiu
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Publication number: 20230009347Abstract: A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. The semiconductor device includes a gate structure that comprises a lower portion and an upper portion. The lower portion wraps around each of the plurality of semiconductor layers. The semiconductor device includes a gate spacer that extends along a sidewall of the upper portion of the gate structure and comprises a first layer and a second layer. The first layer is in contact with a first portion of the sidewall and the second layer is in contact with a second portion of the sidewall.Type: ApplicationFiled: July 9, 2021Publication date: January 12, 2023Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: Shih-Yao Lin, Kuei-Yu Kao, Chen-Ping Chen, Chih-Chung Chiu, Chih-Han Lin, Ming-Ching Chiang, Chao-Cheng Chen
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Publication number: 20220181214Abstract: The disclosure is directed towards semiconductor devices and methods of manufacturing the semiconductor devices. The methods include forming fins in a device region and forming other fins in a multilayer stack of semiconductor materials in a multi-channel device region. A topmost nanostructure may be exposed in the multi-channel device region by removing a sacrificial layer from the top of the multilayer stack. Once removed, a stack of nanostructures are formed from the multilayer stack. A native oxide layer is formed to a first thickness over the topmost nanostructure and to a second thickness over the remaining nanostructures of the stack, the first thickness being greater than the second thickness. A gate dielectric is formed over the fins in the device region. A gate electrode is formed over the gate dielectric in the device region and surrounding the native oxide layer in the multi-channel device region.Type: ApplicationFiled: February 28, 2022Publication date: June 9, 2022Inventors: Shih-Yao Lin, Chih-Chung Chiu, Kuei-Yu Kao, Chen-Ping Chen, Chih-Han Lin
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Patent number: 11264283Abstract: The disclosure is directed towards semiconductor devices and methods of manufacturing the semiconductor devices. The methods include forming fins in a device region and forming other fins in a multilayer stack of semiconductor materials in a multi-channel device region. A topmost nanostructure may be exposed in the multi-channel device region by removing a sacrificial layer from the top of the multilayer stack. Once removed, a stack of nanostructures are formed from the multilayer stack. A native oxide layer is formed to a first thickness over the topmost nanostructure and to a second thickness over the remaining nanostructures of the stack, the first thickness being greater than the second thickness. A gate dielectric is formed over the fins in the device region. A gate electrode is formed over the gate dielectric in the device region and surrounding the native oxide layer in the multi-channel device region.Type: GrantFiled: May 29, 2020Date of Patent: March 1, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shih-Yao Lin, Chih-Chung Chiu, Kuei-Yu Kao, Chen-Ping Chen, Chih-Han Lin
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Patent number: 11243520Abstract: A human-machine interface (HMI) system comprises a local operation device, a display device, a HMI display control device and a communication control device. The local operation device generates a local operation signal. The display device shows a display image corresponding to a display signal. The HMI display control device generates the display signal according to the local operation signal or a remote operation signal. The communication control device comprises a wireless communication connection port for connecting with a remote operation device. The communication control device transmits the local operation signal to the HMI display control device, transmits the display signal to the display device, and selectively transmits the display signal to the remote operation device.Type: GrantFiled: July 26, 2019Date of Patent: February 8, 2022Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chih Chung Chiu, Chih Ming Shen, Ming Ji Dai
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Publication number: 20210375683Abstract: The disclosure is directed towards semiconductor devices and methods of manufacturing the semiconductor devices. The methods include forming fins in a device region and forming other fins in a multilayer stack of semiconductor materials in a multi-channel device region. A topmost nanostructure may be exposed in the multi-channel device region by removing a sacrificial layer from the top of the multilayer stack. Once removed, a stack of nanostructures are formed from the multilayer stack. A native oxide layer is formed to a first thickness over the topmost nanostructure and to a second thickness over the remaining nanostructures of the stack, the first thickness being greater than the second thickness. A gate dielectric is formed over the fins in the device region. A gate electrode is formed over the gate dielectric in the device region and surrounding the native oxide layer in the multi-channel device region.Type: ApplicationFiled: May 29, 2020Publication date: December 2, 2021Inventors: Shih-Yao Lin, Chih-Chung Chiu, Kuei-Yu Kao, Chen-Ping Chen, Chih-Han Lin
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Publication number: 20210296535Abstract: The disclosure illustrates a composite substrate and a method for manufacturing the same, the method including: disposing a mask layer on an upper surface of a substrate; forming a plurality of mask patterns spaced apart from each other to form a plurality of intervals thereamong; filling a dummy metallic material into the intervals; removing the mask patterns to form a mesh-like dummy metallic layer; and removing the dummy metallic layer while depositing a nitride layer so as to form a mesh-like structure confined by the nitride layer and the substrate. The disclosure also illustrates a method for manufacturing a light-emitting device using the composite substrate.Type: ApplicationFiled: June 4, 2021Publication date: September 23, 2021Inventors: Yu Wang, Chiahao Tsai, Qin Wang, Bin Fang, Liangliang Gui, Jinkuang Dong, Shan Wang, Zhaoming Huang, Chih-Chung Chiu, Chi-ming Tsai
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Publication number: 20200383298Abstract: An ear tag module includes a rod member, a spike, a circuit component, and a temperature sensor. The spike is disposed on one side of the rod member, and the circuit component is disposed on another side of the rod member. The temperature sensor is electrically connected to the circuit component. When the spike penetrates an ear, the ear is in contact with a sensing area of the rod member, and the temperature sensor is located in the rod member to detect a temperature of the ear and transmit at least one temperature sensing information to the circuit component.Type: ApplicationFiled: May 27, 2020Publication date: December 10, 2020Applicant: Industrial Technology Research InstituteInventors: Shu-Jung Yang, Yu-Lin Chao, Chih-Chung Chiu, Heng-Chieh Chien
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Publication number: 20200110392Abstract: A human-machine interface (HMI) system comprises a local operation device, a display device, a HMI display control device and a communication control device. The local operation device generates a local operation signal. The display device shows a display image corresponding to a display signal. The HMI display control device generates the display signal according to the local operation signal or a remote operation signal. The communication control device comprises a wireless communication connection port for connecting with a remote operation device. The communication control device transmits the local operation signal to the HMI display control device, transmits the display signal to the display device, and selectively transmits the display signal to the remote operation device.Type: ApplicationFiled: July 26, 2019Publication date: April 9, 2020Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chih Chung CHIU, Chih Ming SHEN, Ming Ji DAI
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Patent number: 10373949Abstract: A semiconductor device includes a semiconductor substrate and a passive component. The passive component is formed on the semiconductor substrate and includes a first polysilicon (poly) layer, a salicide blockage (SAB) layer and a first salicide layer. The SAB layer is formed on the first poly layer. The first salicide layer is formed on the SAB layer.Type: GrantFiled: August 15, 2017Date of Patent: August 6, 2019Assignee: MEDIATEK INC.Inventors: Yan-Liang Ji, Cheng-Hua Lin, Chih-Chung Chiu