Abstract: The quality of a frame sequence is enhanced by a booster engine collaborating with a first stage circuit. The first stage circuit adjusts the quality degradation of the frame sequence when a condition in constrained resources is detected. The quality degradation includes at least one of uneven resolution and uneven frame per second (FPS). The booster engine receives the frame sequence from the first stage circuit, and generates an enhanced frame sequence based on the frame sequence for transmission to a second stage circuit.

Abstract: A method includes forming a first polymer layer to cover a metal pad of a wafer, and patterning the first polymer layer to form a first opening. A first sidewall of the first polymer layer exposed to the first opening has a first tilt angle where the first sidewall is in contact with the metal pad. The method further includes forming a metal pillar in the first opening, sawing the wafer to generate a device die, encapsulating the device die in an encapsulating material, performing a planarization to reveal the metal pillar, forming a second polymer layer over the encapsulating material and the device die, and patterning the second polymer layer to form a second opening. The metal pillar is exposed through the second opening. A second sidewall of the second polymer layer exposed to the second opening has a second tilt angle greater than the first tilt angle.

Abstract: A method for operating an emergency charging device includes when a mutual charging switch of the emergency charging device is triggered, setting a plurality of batteries whose power is lower than a predetermined threshold as a target battery group, selecting a battery with a highest capacity from the target battery group as a battery to be recharged, selecting a battery with a capacity lower than the battery to be recharged from the target battery group as a discharge battery, and charging the battery to be recharged from the discharge battery.

Abstract: An antenna assembly includes a patch antenna, a metal layer, and a feed-in signal layer. The metal layer is disposed on a side of the patch antenna and includes a first slot and a second slot. The feed-in signal layer is disposed on a side of the metal layer opposite the second antenna and includes a transmitting port, a receiving port, a hybrid coupler, and two microstrips. The transmitting port and the receiving port are connected to the hybrid coupler, and the two microstrips are extended in the direction away from the hybrid coupler. Projections of two ends of the two microstrips onto the metal layer are overlapped with the first slot and the second slot. An antenna array is also mentioned.

Abstract: Semiconductor structures and formation processes thereof are provided. A semiconductor structure of the present disclosure includes a semiconductor substrate, a plurality of transistors disposed on the semiconductor substrate and comprising a plurality of gate structures extending lengthwise along a first direction, a metallization layer disposed over the plurality of transistors, the metallization layer comprising a plurality of metal layers and a plurality of contact vias, a dielectric layer over the metallization layer, a plurality of dielectric fins extending parallel along the first direction and disposed over the dielectric layer, a semiconductor layer disposed conformally over the plurality of dielectric fins, a source contact and a drain contact disposed directly on the semiconductor layer, and a gate structure disposed over the semiconductor layer and between the source contact and the drain contact.

Abstract: An image displaying device includes a planar display panel and a light penetrating unit. The planar display panel displays a plane image. The planar display panel at least includes a first pixel group, a second pixel group and a third pixel group. The second pixel group is located between the first pixel group and the third pixel group. When vision passes through the light penetrating unit toward the planar display panel, the vision acquires a second distance of a second imaging position within the plane image relevant to the second pixel group relative to the planar display panel being greater than a first distance of a first imaging position within the plane image relevant to the first pixel group relative to the planar display panel and a third distance of a third imaging position within the plane image relevant to the third pixel group relative to the planar display panel.

Abstract: A head-mounted device and a retractable headband are provided. The head-mounted device includes a host, a retractable headband, and an earphone. The host has a first connection part and a second connection part located on two opposite sides. The retractable headband has an earphone connection part and a first connection end and a second connection end located on two opposite sides. The first connection end is connected to the first connection part. The second connection end is connected to the second connection part. When the retractable headband is elongated by an elongation amount, a change in a distance between the earphone connection part and the first connection end is less than half of the elongation amount. The earphone is connected to the earphone connection part.

Abstract: A landing/takeoff response system and method for an UAV, including a fuselage having a housing and a flight power module connected to the fuselage, are provided. The system includes a first sensor for detecting a first sensing information, at least one second sensor for detecting a second sensing information, and a processing unit coupled to the first sensor and the second sensor. The first sensor is disposed on a bottom portion of the housing at a position below a center of gravity of the UAV. The second sensor is disposed on a side portion of the housing adjacent to the bottom portion. The processing unit is configured to: determine whether the first sensing information satisfies a first contact condition to determine a landing/takeoff operation of the UAV; and determine whether the second sensing information satisfies a second contact condition to determine an on/off status of the flight power module.

Abstract: An unmanned vehicle includes a body and a plurality of battery packs. The battery packs are detachably stacked on the body, wherein the body sequentially uses the power of the battery packs in an anti-gravity direction.

Abstract: An electronic device includes a metal back cover and an antenna module. The metal back cover includes a slot. The antenna module is located in the metal back cover. The antenna module includes a first radiator, second radiator, third radiator, fourth radiator, and fifth radiator. The first radiator has a feeding end. The second radiator connected to the first radiator has a contact portion which is connected to the metal back cover. The third radiator is connected to the second radiator and is located beside the first radiator. The third radiator has a first grounding terminal. The fourth radiator is connected to the second radiator and has a second grounding terminal. The fifth radiator is connected to the third radiator and the fourth radiator. Distances between the feeding end and the slot, the first grounding terminal and the slot, and the second grounding terminal and the slot all range from 3.5 mm to 10 mm.

Abstract: An interconnect structure and methods of forming the same are described. In some embodiments, the structure includes a first intermetal dielectric (IMD) layer disposed over a plurality of conductive features and a first passive component disposed on the first IMD layer in a first region of the substrate. The structure further includes a second passive component disposed on the first IMD layer in a second region of the substrate. The second passive component includes a first conductive layer, and the first conductive layer has a first thickness. The structure further includes a second IMD layer disposed on the first passive component in the first region and on the second passive component and a portion of the first IMD layer in the second region. The second IMD layer has a second thickness ranging from about five times to about 20 times the first thickness.

Abstract: An antenna module disposed on a substrate having a first and a second surface opposite to each other includes a microstrip line, a first radiator, a ground radiator and a ground plane. The microstrip line, the first radiator and the ground radiator are disposed on the first surface. The microstrip line includes a first and a second end opposite to each other. The first end includes a first feeding end. The first radiator is connected to the second end of the microstrip line. The ground radiator surrounds the microstrip line and the first radiator and has a first opening and two opposite grounding ends. The first end of the microstrip line is located in the first opening. A gap is formed between each grounding end and the first feeding end. The ground plane is disposed on the second surface. The ground radiator is connected to the ground plane.

Abstract: An antenna module includes a transceiver chip, a transmitting array antenna, a receiving array antenna, two bandpass filters, and two capacitors. The transmitting array antenna and the receiving array antenna are symmetrically disposed at the two opposite sides of the transceiver chip. One of the bandpass filters is disposed between the transceiver chip and the transmitting array antenna and connected to the transceiver chip and the transmitting array antenna. The other bandpass filter is disposed between the transceiver chip and the receiving array antenna and connected to the transceiver chip and the receiving array antenna. One of the capacitors is disposed between the transmitting array antenna and the corresponding bandpass filter and connected to the transmitting array antenna and the corresponding bandpass filter. The other capacitor is disposed between the receiving array antenna and the corresponding bandpass filter and connected to the receiving array antenna and the corresponding bandpass filter.

Abstract: An electronic device includes a metal back cover and an antenna module. The metal back cover includes a slot. The antenna module is located in the metal back cover. The antenna module includes a first radiator, second radiator, third radiator, fourth radiator, and fifth radiator. The first radiator has a feeding end. The second radiator connected to the first radiator has a contact portion which is connected to the metal back cover. The third radiator is connected to the second radiator and is located beside the first radiator. The third radiator has a first grounding terminal. The fourth radiator is connected to the second radiator and has a second grounding terminal. The fifth radiator is connected to the third radiator and the fourth radiator. Distances between the feeding end and the slot, the first grounding terminal and the slot, and the second grounding terminal and the slot all range from 3.5 mm to 10 mm.

Abstract: An interconnect structure and methods of forming the same are described. In some embodiments, the structure includes a first intermetal dielectric (IMD) layer disposed over a plurality of conductive features and a first passive component disposed on the first IMD layer in a first region of the substrate. The structure further includes a second passive component disposed on the first IMD layer in a second region of the substrate. The second passive component includes a first conductive layer, and the first conductive layer has a first thickness. The structure further includes a second IMD layer disposed on the first passive component in the first region and on the second passive component and a portion of the first IMD layer in the second region. The second IMD layer has a second thickness ranging from about five times to about 20 times the first thickness.

Abstract: A method includes providing a substrate of a first conductivity type, the substrate including a first circuit region and a second circuit region; forming a first well region of a second conductivity type in the first circuit region of the substrate; forming a first doped region of the second conductivity type in the first well region; forming a diode in the second circuit region of the substrate; forming a first transistor and a second transistor over the substrate in the first circuit region and the second circuit region, respectively; forming a discharge structure over the substrate to electrically couple the first doped region to the diode; and forming a metallization layer over the discharge structure to electrically couple the first transistor to the second transistor subsequent to the forming of the diode, wherein charges accumulated in the first well region are drained to the substrate through the discharge structure.

Abstract: An antenna module disposed on a substrate having a first and a second surface opposite to each other includes a microstrip line, a first radiator, a ground radiator and a ground plane. The microstrip line, the first radiator and the ground radiator are disposed on the first surface. The microstrip line includes a first and a second end opposite to each other. The first end includes a first feeding end. The first radiator is connected to the second end of the microstrip line. The ground radiator surrounds the microstrip line and the first radiator and has a first opening and two opposite grounding ends. The first end of the microstrip line is located in the first opening. A gap is formed between each grounding end and the first feeding end. The ground plane is disposed on the second surface. The ground radiator is connected to the ground plane.

Abstract: A plurality of openings is formed in a dielectric layer formed on a semiconductor substrate. The plurality of openings comprises a first opening extending to the semiconductor substrate, a second opening extending to a first depth that is substantially less than a thickness of the dielectric layer, and a third opening extending to a second depth that is substantially greater than the first depth. A multi-layer gate electrode is formed in the first opening. A thin resistor structure is formed in the second opening, and a connection structure is formed in the third opening, by filling the second and third openings substantially simultaneously with a resistor metal.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises a substrate, a fin structure, a metal gate and a first polysilicon strip. The fin structure is on the substrate. The metal gate is over the fin structure and is substantially perpendicular to the fin structure. The first polysilicon strip is at a first edge of the fin structure and is substantially parallel to the metal gate.

Abstract: The present disclosure relates a back-end-of-the-line (BEOL) metallization stack having an air gap disposed between adjacent metal interconnect features, which provides for an inter-level dielectric material with a low dielectric constant. In some embodiments, the BEOL metallization stack has an inter-level dielectric (ILD) layer disposed over a substrate. A metal interconnect layer is disposed within the ILD layer, and an air gap is arranged disposed within the ILD layer at a position between a first feature and a second feature of the metal interconnect layer. The air gap has an upper surface with a first curve that meets a second curve at a peak arranged below a top of the metal interconnect layer. The first curve becomes steeper as a distance from the peak decreases and the second curve becomes steeper as a distance from the peak decreases.