Patents by Inventor Chih-Fu Chang
Chih-Fu Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240379530Abstract: An interconnect structure and methods of forming the same are described. In some embodiments, the structure includes a first intermetal dielectric (IMD) layer disposed over a plurality of conductive features and a first passive component disposed on the first IMD layer in a first region of the substrate. The structure further includes a second passive component disposed on the first IMD layer in a second region of the substrate. The second passive component includes a first conductive layer, and the first conductive layer has a first thickness. The structure further includes a second IMD layer disposed on the first passive component in the first region and on the second passive component and a portion of the first IMD layer in the second region. The second IMD layer has a second thickness ranging from about five times to about 20 times the first thickness.Type: ApplicationFiled: July 25, 2024Publication date: November 14, 2024Inventors: Yao-Jen TSAI, Chih-Fu CHANG, Chin-Yuan KO, Sheng Chiang HUNG
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Publication number: 20240378295Abstract: An embodiment of the invention provides a data authentication device. The data authentication device may include a main memory, a backup memory, a platform control hub (PCH) and an embedded controller (EC). The main memory may be configured to store data. The backup memory may be configured to back up the data stored in the main memory. The PCH is coupled to the main memory and generates a write command to write a first data image to the main memory, wherein the first data image comprises updated data and a digital signature. The EC is coupled to the main memory, the backup memory and the PCH and obtains the first data image from the PCH. When the EC detects a write command, the EC may perform an authentication for the updated data based on the first data image or a second data image corresponding to the first data image.Type: ApplicationFiled: May 3, 2024Publication date: November 14, 2024Inventors: Ming-Hung WU, Hao-Yang CHANG, Chih-Hung HUANG, Kang-Fu CHIU
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Publication number: 20240345405Abstract: A head-mounted display device includes a front-end assembly, a wearing assembly and a light-shielding face mask. The wearing assembly is assembled to the front-end assembly to position the front-end assembly on a user's face. The light-shielding face mask includes a frame and a cover. The frame is connected to the front-end assembly. The cover is flexible and connected to the frame to cover the user's eyes. The cover has a forehead portion corresponding to the user's forehead and a pair of eye tail portions respectively corresponding to a pair of eye tails of the user. The forehead portion pushed by the user's forehead drives the pair of eye tail portions to approach the pair of eye tails of the user respectively.Type: ApplicationFiled: November 9, 2023Publication date: October 17, 2024Applicant: HTC CorporationInventors: Li-Hsun Chang, Kuan-Ying Ou, Chen-Fu Chang, Chih-Hsiang Hsieh, Yu-Hsun Chung
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Publication number: 20240313046Abstract: A method for fabricating a semiconductor device includes the steps of forming a fin-shaped structure on a substrate, forming a first trench and a second trench in the fin-shaped structure, forming a first dielectric layer in the first trench and the second trench, removing part of the first dielectric layer, forming a second dielectric layer in the first trench and the second trench to form a first single diffusion break (SDB) structure and a second SDB structure, and then forming a gate structure on the fin-shaped structure, the first SDB structure, and the second SDB structure.Type: ApplicationFiled: April 13, 2023Publication date: September 19, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Guang-Yu Lo, Chun-Tsen Lu, Chung-Fu Chang, Chih-Shan Wu, Yu-Hsiang Lin, Wei-Hao Chang
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Publication number: 20240294085Abstract: A mobile charging device includes a charging host, two charging plates, a mobile parking plate and a charging gun. The charging host includes two electrode blocks having different electrical properties. The two charging plates are in contact with the two electrode blocks, respectively. The mobile parking plate includes a parking plate body having a first surface and a second surface, and two conductive contact blocks disposed on the second surface, wherein the first surface is adapted to park the vehicle. The charging gun is disposed on the parking plate body and electrically connected with two conductive contact blocks. When the mobile parking plate is in the first position, the charging gun, the two conductive contact blocks, the two charging plates and the charging host are conducted with each other, and the vehicle parked on the parking plate body can be charged through the charging gun.Type: ApplicationFiled: August 31, 2023Publication date: September 5, 2024Inventors: CHIH-YING CHENG, CHI-FU CHANG
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Patent number: 12080943Abstract: An antenna module disposed on a substrate having a first and a second surface opposite to each other includes a microstrip line, a first radiator, a ground radiator and a ground plane. The microstrip line, the first radiator and the ground radiator are disposed on the first surface. The microstrip line includes a first and a second end opposite to each other. The first end includes a first feeding end. The first radiator is connected to the second end of the microstrip line. The ground radiator surrounds the microstrip line and the first radiator and has a first opening and two opposite grounding ends. The first end of the microstrip line is located in the first opening. A gap is formed between each grounding end and the first feeding end. The ground plane is disposed on the second surface. The ground radiator is connected to the ground plane.Type: GrantFiled: February 22, 2022Date of Patent: September 3, 2024Assignee: PEGATRON CORPORATIONInventors: Chien-Yi Wu, Tse-Hsuan Wang, Chih-Fu Chang, Chao-Hsu Wu, Shih-Keng Huang, Hau Yuen Tan
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Publication number: 20240266336Abstract: An embodiment is a structure including a first package including a first die, and a molding compound at least laterally encapsulating the first die, a second package bonded to the first package with a first set of conductive connectors, the second package comprising a second die, and an underfill between the first package and the second package and surrounding the first set of conductive connectors, the underfill having a first portion extending up along a sidewall of the second package, the first portion having a first sidewall, the first sidewall having a curved portion and a planar portion.Type: ApplicationFiled: April 17, 2024Publication date: August 8, 2024Inventors: Hsi-Kuei Cheng, Ching Fu Chang, Chih-Kang Han, Hsin-Chieh Huang
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Patent number: 12044351Abstract: A rotary device with automatic reset function for precise stopping and holding of a viewable rotating element without free play or slop remaining includes a conversion assembly, and a power assembly with output element and sensing assembly. The conversion assembly comprises a light-shielding structure with the light-shielding structure on the extension part. The power assembly with output element can drive the extension part to rotate synchronously with the light-shielding structure. The detachable sensing assembly overlaps the rotation path of the light-shielding structure, and the conversion assembly rotates at different angles so that the light-shielding structure and the sensing assembly will match at certain angles, so as to trigger a sensing signal and call up the output element. A display screen includes the rotary device with automatic reset function and a display assembly.Type: GrantFiled: September 1, 2022Date of Patent: July 23, 2024Assignees: Futaijing Precision Electronics (Yantai) Co., Ltd., HON HAI PRECISION INDUSTRY CO., LTD.Inventors: Yu-Sheng Chang, Chi-Cheng Wen, Chih-Cheng Lee, Wen-Bin Huang, Tsung-Hsin Wu, Yu-Chih Cheng, Hsiu-Fu Li
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Patent number: 12040561Abstract: An antenna module includes a transceiver chip, a transmitting array antenna, a receiving array antenna, two bandpass filters, and two capacitors. The transmitting array antenna and the receiving array antenna are symmetrically disposed at the two opposite sides of the transceiver chip. One of the bandpass filters is disposed between the transceiver chip and the transmitting array antenna and connected to the transceiver chip and the transmitting array antenna. The other bandpass filter is disposed between the transceiver chip and the receiving array antenna and connected to the transceiver chip and the receiving array antenna. One of the capacitors is disposed between the transmitting array antenna and the corresponding bandpass filter and connected to the transmitting array antenna and the corresponding bandpass filter. The other capacitor is disposed between the receiving array antenna and the corresponding bandpass filter and connected to the receiving array antenna and the corresponding bandpass filter.Type: GrantFiled: October 17, 2022Date of Patent: July 16, 2024Assignee: PEGATRON CORPORATIONInventors: Tse-Hsuan Wang, Chien-Yi Wu, Chih-Fu Chang, Chao-Hsu Wu, Chih-Yi Chiu, Wei-Han Yen, Tsung-Chi Tsai, Shih-Keng Huang, I-Shu Lee
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Publication number: 20230093423Abstract: An electronic device includes a metal back cover and an antenna module. The metal back cover includes a slot. The antenna module is located in the metal back cover. The antenna module includes a first radiator, second radiator, third radiator, fourth radiator, and fifth radiator. The first radiator has a feeding end. The second radiator connected to the first radiator has a contact portion which is connected to the metal back cover. The third radiator is connected to the second radiator and is located beside the first radiator. The third radiator has a first grounding terminal. The fourth radiator is connected to the second radiator and has a second grounding terminal. The fifth radiator is connected to the third radiator and the fourth radiator. Distances between the feeding end and the slot, the first grounding terminal and the slot, and the second grounding terminal and the slot all range from 3.5 mm to 10 mm.Type: ApplicationFiled: August 12, 2022Publication date: March 23, 2023Applicant: PEGATRON CORPORATIONInventors: Chien-Yi Wu, Hau Yuen Tan, Chao-Hsu Wu, Chen-Kuang Wang, Chih-Fu Chang, Tsung-Chi Tsai, Shih-Keng Huang, Tse-Hsuan Wang, Sheng-Chin Hsu
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Publication number: 20230035580Abstract: An interconnect structure and methods of forming the same are described. In some embodiments, the structure includes a first intermetal dielectric (IMD) layer disposed over a plurality of conductive features and a first passive component disposed on the first IMD layer in a first region of the substrate. The structure further includes a second passive component disposed on the first IMD layer in a second region of the substrate. The second passive component includes a first conductive layer, and the first conductive layer has a first thickness. The structure further includes a second IMD layer disposed on the first passive component in the first region and on the second passive component and a portion of the first IMD layer in the second region. The second IMD layer has a second thickness ranging from about five times to about 20 times the first thickness.Type: ApplicationFiled: January 25, 2022Publication date: February 2, 2023Inventors: Yao-Jen TSAI, Chih-Fu CHANG, Sheng Chiang HUNG, Chin-Yuan KO
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Publication number: 20220406608Abstract: A method includes providing a substrate of a first conductivity type, the substrate including a first circuit region and a second circuit region; forming a first well region of a second conductivity type in the first circuit region of the substrate; forming a first doped region of the second conductivity type in the first well region; forming a diode in the second circuit region of the substrate; forming a first transistor and a second transistor over the substrate in the first circuit region and the second circuit region, respectively; forming a discharge structure over the substrate to electrically couple the first doped region to the diode; and forming a metallization layer over the discharge structure to electrically couple the first transistor to the second transistor subsequent to the forming of the diode, wherein charges accumulated in the first well region are drained to the substrate through the discharge structure.Type: ApplicationFiled: June 18, 2021Publication date: December 22, 2022Inventors: YAO-JEN TSAI, KENG-HUI LIAO, CHIH-KAI YANG, CHIH-FU CHANG, CHIA-JEN LEU, CHIN-YUAN KO
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Publication number: 20220344804Abstract: An antenna module disposed on a substrate having a first and a second surface opposite to each other includes a microstrip line, a first radiator, a ground radiator and a ground plane. The microstrip line, the first radiator and the ground radiator are disposed on the first surface. The microstrip line includes a first and a second end opposite to each other. The first end includes a first feeding end. The first radiator is connected to the second end of the microstrip line. The ground radiator surrounds the microstrip line and the first radiator and has a first opening and two opposite grounding ends. The first end of the microstrip line is located in the first opening. A gap is formed between each grounding end and the first feeding end. The ground plane is disposed on the second surface. The ground radiator is connected to the ground plane.Type: ApplicationFiled: February 22, 2022Publication date: October 27, 2022Applicant: PEGATRON CORPORATIONInventors: Chien-Yi Wu, Tse-Hsuan Wang, Chih-Fu Chang, Chao-Hsu Wu, Shih-Keng Huang, Hau Yuen Tan
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Patent number: 10686030Abstract: A plurality of openings is formed in a dielectric layer formed on a semiconductor substrate. The plurality of openings comprises a first opening extending to the semiconductor substrate, a second opening extending to a first depth that is substantially less than a thickness of the dielectric layer, and a third opening extending to a second depth that is substantially greater than the first depth. A multi-layer gate electrode is formed in the first opening. A thin resistor structure is formed in the second opening, and a connection structure is formed in the third opening, by filling the second and third openings substantially simultaneously with a resistor metal.Type: GrantFiled: September 18, 2017Date of Patent: June 16, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiu-Jung Yen, Jen-Pan Wang, Yu-Hong Pan, Chih-Fu Chang
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Patent number: 10153355Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises a substrate, a fin structure, a metal gate and a first polysilicon strip. The fin structure is on the substrate. The metal gate is over the fin structure and is substantially perpendicular to the fin structure. The first polysilicon strip is at a first edge of the fin structure and is substantially parallel to the metal gate.Type: GrantFiled: December 4, 2015Date of Patent: December 11, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Sheng Chiang Hung, Tsung-Che Lu, Chih-Fu Chang
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Patent number: 10062603Abstract: The present disclosure relates a back-end-of-the-line (BEOL) metallization stack having an air gap disposed between adjacent metal interconnect features, which provides for an inter-level dielectric material with a low dielectric constant. In some embodiments, the BEOL metallization stack has an inter-level dielectric (ILD) layer disposed over a substrate. A metal interconnect layer is disposed within the ILD layer, and an air gap is arranged disposed within the ILD layer at a position between a first feature and a second feature of the metal interconnect layer. The air gap has an upper surface with a first curve that meets a second curve at a peak arranged below a top of the metal interconnect layer. The first curve becomes steeper as a distance from the peak decreases and the second curve becomes steeper as a distance from the peak decreases.Type: GrantFiled: July 29, 2016Date of Patent: August 28, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ru-Shang Hsiao, Chih-Fu Chang, Jen-Pan Wang
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Patent number: 9978744Abstract: A passive device and method of fabricating the passive device are disclosed herein. The capacitor structure incorporates a resistor and a capacitor. An exemplary method includes receiving a substrate that has undergone front end of line (FEOL) processing, and performing back end of line (BEOL) processing on the substrate, wherein a capacitor structure is formed over the substrate during the BEOL processing, the capacitor structure incorporating a resistor with a capacitor. The BEOL processing can include performing a first metallization process to form a bottom plate of the capacitor structure; forming a dielectric spacer of the capacitor structure over the bottom plate; forming a top plate of the capacitor structure over the dielectric spacer; and performing a second metallization process to form contacts coupled to the top plate and the bottom plate of the capacitor structure.Type: GrantFiled: May 25, 2016Date of Patent: May 22, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Fu Chang, Jen-Pan Wang
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Publication number: 20180026091Abstract: A plurality of openings is formed in a dielectric layer formed on a semiconductor substrate. The plurality of openings comprises a first opening extending to the semiconductor substrate, a second opening extending to a first depth that is substantially less than a thickness of the dielectric layer, and a third opening extending to a second depth that is substantially greater than the first depth. A multi-layer gate electrode is formed in the first opening. A thin resistor structure is formed in the second opening, and a connection structure is formed in the third opening, by filling the second and third openings substantially simultaneously with a resistor metal.Type: ApplicationFiled: September 18, 2017Publication date: January 25, 2018Inventors: Hsiu-Jung Yen, Jen-Pan Wang, Yu-Hong Pan, Chih-Fu Chang
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Patent number: 9768243Abstract: A plurality of openings is formed in a dielectric layer formed on a semiconductor substrate. The plurality of openings comprises a first opening extending to the semiconductor substrate, a second opening extending to a first depth that is substantially less than a thickness of the dielectric layer, and a third opening extending to a second depth that is substantially greater than the first depth. A multi-layer gate electrode is formed in the first opening. A thin resistor structure is formed in the second opening, and a connection structure is formed in the third opening, by filling the second and third openings substantially simultaneously with a resistor metal.Type: GrantFiled: July 5, 2013Date of Patent: September 19, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiu-Jung Yen, Jen-Pan Wang, Yu-Hong Pan, Chih-Fu Chang
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Patent number: D1042441Type: GrantFiled: February 7, 2023Date of Patent: September 17, 2024Assignee: Dell Products L.P.Inventors: Chih-Chieh Chang, Jihun Yeom, Chien-Cheng Chen, Ya Sang Fong, Hsuan-Ping Weng, Jui Fu Wu, Shang-Zu Hsieh