Patents by Inventor Chih-Hang Tung

Chih-Hang Tung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Thinning process using metal-assisted chemical etching
    Patent number: 9893046
    Abstract: Methods for forming a chip package are provided. The method includes providing at least one carrier substrate including first semiconductor dies mounted thereon. The method also includes forming a first noble metal layer including nanopores irregularly distributed therein to cover each one of the first semiconductor dies. The method further includes immersing the carrier substrate with the first semiconductor dies into an etchant solution including a fluoride etchant and an oxidizing agent, so that each one of the first semiconductor dies covered by the first noble metal layer is thinned.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: February 13, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Su-Chun Yang, Yi-Li Hsiao, Tung-Liang Shao, Chih-Hang Tung, Chen-Hua Yu
  • Manufacturing method of interconnect structure
    Patent number: 9881888
    Abstract: A conductive interconnect structure includes a contact pad; a conductive body connected to the contact pad at a first end; and a conductive layer positioned on a second end of the conductive body. The conductive body has a longitudinal direction perpendicular to a surface of the contact pad. The conductive body has an average grain size (a) on a cross sectional plane (Plane A) whose normal is perpendicular to the longitudinal direction of the conductive body. The conductive layer has an average grain size (b) on Plane A. The conductive body and the conductive layer are composed of same material, and the average grain size (a) is greater than the average grain size (b).
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: January 30, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Meng-Tse Chen, Hsiu-Jen Lin, Chih-Wei Lin, Ming-Da Cheng, Chih-Hang Tung, Chung-Shi Liu
  • THINNING PROCESS USING METAL-ASSISTED CHEMICAL ETCHING
    Publication number: 20180012880
    Abstract: Methods for forming a chip package are provided. The method includes providing at least one carrier substrate including first semiconductor dies mounted thereon. The method also includes forming a first noble metal layer including nanopores irregularly distributed therein to cover each one of the first semiconductor dies. The method further includes immersing the carrier substrate with the first semiconductor dies into an etchant solution including a fluoride etchant and an oxidizing agent, so that each one of the first semiconductor dies covered by the first noble metal layer is thinned.
    Type: Application
    Filed: July 8, 2016
    Publication date: January 11, 2018
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Su-Chun YANG, Yi-Li HSIAO, Tung-Liang SHAO, Chih-Hang TUNG, Chen-Hua YU
  • SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE THEREOF
    Publication number: 20170373050
    Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a device includes coupling a first semiconductor device to a second semiconductor device by spacers. The first semiconductor device has first contact pads disposed thereon, and the second semiconductor device has second contact pads disposed thereon. The method includes forming an immersion interconnection between the first contact pads of the first semiconductor device and the second contact pads of the second semiconductor device.
    Type: Application
    Filed: June 27, 2016
    Publication date: December 28, 2017
    Inventors: Tung-Liang Shao, Yi-Li Hsiao, Hsiao-Yun Chen, Chih-Hang Tung, Chen-Hua Yu
  • Solder bump stretching method and device for performing the same
    Patent number: 9842817
    Abstract: A wafer-level pulling method includes securing a top holder to a plurality of chips; and securing a bottom holder to a wafer, wherein the plurality of chips are bonded to the wafer by a plurality of solder bumps. The wafer-level pulling method further includes softening the plurality of solder bumps; and stretching the plurality of softened solder bumps.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: December 12, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Su-Chun Yang, Yi-Li Hsiao, Chih-Hang Tung, Chen-Hua Yu
  • System and Method for Immersion Bonding
    Publication number: 20170330855
    Abstract: A representative system and method for manufacturing stacked semiconductor devices includes disposing an aqueous alkaline solution between a first semiconductor device and a second semiconductor device prior to bonding. In a representative implementation, first and second semiconductor devices may be hybrid bonded to one another, where dielectric features of the first semiconductor device are bonded to dielectric features of the second semiconductor device, and metal features of the first semiconductor device are bonded to metal features of the second semiconductor device. Immersion bonds so formed demonstrate a substantially lower incidence of delamination associated with bond defects.
    Type: Application
    Filed: May 13, 2016
    Publication date: November 16, 2017
    Inventors: Chih-Hang Tung, Su-Chun Yang, Tung-Liang Shao, Chen-Hua Yu
  • Non-planar transistors and methods of fabrication thereof
    Patent number: 9735276
    Abstract: Non-planar transistors and methods of fabrication thereof are described. In an embodiment, a method of forming a non-planar transistor includes forming a channel region on a first portion of a semiconductor fin, the semiconductor fin having a top surface and sidewalls. A gate electrode is formed over the channel region of the semiconductor fin, and an in-situ doped semiconductor layer is grown on the top surface and the sidewalls of the semiconductor fin on opposing sides of the gate electrode using a selective epitaxial growth process. At least a part of the doped semiconductor layer is converted to form a dopant rich region.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: August 15, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hang Tung, Chin-Hsiang Lin, Cheng-Hung Chang, Sey-Ping Sun
  • Multi-Strike Process for Bonding
    Publication number: 20170194278
    Abstract: A method includes performing a first strike process to strike a metal bump of a first package component against a metal pad of a second package component. A first one of the metal bump and the metal pad includes copper. A second one of the metal bump and the metal pad includes aluminum. The method further includes performing a second strike process to strike the metal bump against the metal pad. An annealing is performed to bond the metal bump on the metal pad.
    Type: Application
    Filed: February 15, 2017
    Publication date: July 6, 2017
    Inventors: Tung-Liang Shao, Chih-Hang Tung, Wen-Lin Shih, Hsiao-Yun Chen, Chen-Hua Yu
  • Method of multi-chip wafer level packaging
    Patent number: 9679882
    Abstract: A method of multi-chip wafer level packaging comprises attaching a first semiconductor die to a top side of a wafer, forming a first reconfigured wafer by embedding the first semiconductor die into a first photo-sensitive material layer, forming a first group of through assembly vias in the first photo-sensitive material layer, attaching a second semiconductor die to the first photo-sensitive material layer, forming a second photo-sensitive material layer on top of the first photo-sensitive material layer, wherein the second semiconductor die is embedded in the second photo-sensitive material layer and forming a second group of through assembly vias in the second photo-sensitive material layer.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: June 13, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hang Tung, Chun Hui Yu, Chen-Hua Yu, Da-Yuan Shih
  • SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20170154881
    Abstract: The present disclosure relates to a semiconductor device and method of manufacturing the same. The method for manufacturing a semiconductor device includes: attaching a carrier wafer to a front side of a top die wafer; thinning a back side of the top die wafer, the back side of the top die wafer being opposite to the front side the top die wafer; singulating the carrier wafer and the top die wafer whereby singulated dies attached to singulated carrier dies are formed; and bonding back side of each of the singulated dies to a front side of a bottom die wafer.
    Type: Application
    Filed: November 30, 2015
    Publication date: June 1, 2017
    Inventors: TUNG-LIANG SHAO, CHIH-HANG TUNG, CHEN-HUA YU
  • Multi-strike process for bonding
    Patent number: 9576929
    Abstract: A method includes performing a first strike process to strike a metal bump of a first package component against a metal pad of a second package component. A first one of the metal bump and the metal pad includes copper. A second one of the metal bump and the metal pad includes aluminum. The method further includes performing a second strike process to strike the metal bump against the metal pad. An annealing is performed to bond the metal bump on the metal pad.
    Type: Grant
    Filed: January 18, 2016
    Date of Patent: February 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tung-Liang Shao, Chih-Hang Tung, Wen-Lin Shih, Hsiao-Yun Chen, Chen-Hua Yu
  • Functional block stacked 3DIC and method of making same
    Patent number: 9564420
    Abstract: An embodiment device package includes a fan-out redistribution layer (RDL), a device over and bonded to the fan-out RDL, and a molding compound over the fan-out RDL and extending along sidewalls of the device. The device includes a first functional tier having a first metallization layer and a second functional tier having a second metallization layer. The second functional tier is bonded to the first functional tier. The device further includes an interconnect structure electrically connecting the first metallization layer to the second metallization layer. The interconnect structure includes an inter-tier via (ITV) at least partially disposed in both the first functional tier and the second functional tier, and the ITV contacts the first metallization layer.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: February 7, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Kuo-Chung Yee, Chih-Hang Tung
  • SOLDER BUMP STRETCHING METHOD FOR FORMING A SOLDER BUMP JOINT IN A DEVICE
    Publication number: 20170012019
    Abstract: A method of producing a solder bump joint includes heating a solder bump comprising tin above a melting temperature of the solder bump, wherein the solder bumps comprises eutectic Sn—Bi compound, and the eutectic Sn-Bi compound is free of Ag. The method further includes stretching the solder bump to increase a height of the solder bump, wherein stretching the solder bump forms lamellar structures having a contact angle of less than 90°. The method further includes cooling down the solder bump.
    Type: Application
    Filed: September 26, 2016
    Publication date: January 12, 2017
    Inventors: Su-Chun YANG, Chung-Jung WU, Hsiao-Yun CHEN, Yi-Li HSIAO, Chih-Hang TUNG, Da-Yuan SHIH, Chen-Hua YU
  • Semiconductor Device And Bump Formation Process
    Publication number: 20170005051
    Abstract: A semiconductor device includes a solder bump overlying and electrically connected to a pad region, and a metal cap layer formed on at least a portion of the solder bump. The metal cap layer has a melting temperature greater than the melting temperature of the solder bump.
    Type: Application
    Filed: September 19, 2016
    Publication date: January 5, 2017
    Inventors: Yi-Li Hsiao, Chen-Hua Yu, Shin-Puu Jeng, Chih-Hang Tung, Cheng-Chang Wei
  • Thermally enhanced structure for multi-chip device
    Patent number: 9530715
    Abstract: A multi-chip semiconductor device comprises a thermally enhanced structure, a first semiconductor chip, a second semiconductor chip, an encapsulation layer formed on top of the first semiconductor chip and the second semiconductor chip. The multi-chip semiconductor device further comprises a plurality of thermal vias formed in the encapsulation layer. The thermally enhanced structure comprises a heat sink block attached to a first semiconductor die. The heat sink block may further comprise a variety of thermal vias and thermal openings. By employing the thermal enhanced structure, the thermal performance of the multi-chip semiconductor device can be improved.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: December 27, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chih-Hang Tung, Tung-Liang Shao
  • Two-step direct bonding processes and tools for performing the same
    Patent number: 9521795
    Abstract: A method includes placing a plurality of first package components over second package components, which are included in a third package component. First metal connectors in the first package components are aligned to respective second metal connectors of the second package components. After the plurality of first package components is placed, a metal-to-metal bonding is performed to bond the first metal connectors to the second metal connectors.
    Type: Grant
    Filed: April 19, 2013
    Date of Patent: December 13, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Li Hsiao, Da-Yuan Shih, Chih-Hang Tung, Chen-Hua Yu
  • Solder bump joint in a device including lamellar structures
    Patent number: 9475145
    Abstract: A method includes heating a solder bump above a melting temperature of the solder bump. The solder bump is stretched to increase a height of the solder bump. The solder bump is cooled down to form a solder bump joint in an electrical device.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: October 25, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Su-Chun Yang, Chung-Jung Wu, Hsiao-Yun Chen, Yi-Li Hsiao, Chih-Hang Tung, Da-Yuan Shih, Chen-Hua Yu
  • Copper-containing layer on under-bump metallization layer
    Patent number: 9472524
    Abstract: A semiconductor device includes an under-bump metallization (UBM) layer over a substrate. The semiconductor device also includes a copper-containing layer having a base portion over the UBM layer. The semiconductor device further includes a solder bump over the UBM layer and over the copper-containing layer. The base portion is embedded in the solder bump. The copper-containing layer has a cylindrical shape and includes at least two segments separated by at least two openings. A first total area (A) of the at least two openings is greater than about 3% of a second total area (B) of the at least two segments. The first total area (A) is less than about 70% of the second total area (B) of the at least two segments.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: October 18, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Feng Chen, Chun-Hung Lin, Han-Ping Pu, Chih-Hang Tung, Kai-Chiang Wu, Ming-Che Ho
  • Semiconductor device and bump formation process
    Patent number: 9455183
    Abstract: A semiconductor device includes a solder bump overlying and electrically connected to a pad region, and a metal cap layer formed on at least a portion of the solder bump. The metal cap layer has a melting temperature greater than the melting temperature of the solder bump.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: September 27, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Li Hsiao, Chen-Hua Yu, Shin-Puu Jeng, Chih-Hang Tung, Cheng-Chang Wei
  • INTERCONNECT STRUCTURE AND MANUFACTURING METHOD THEREOF
    Publication number: 20160211234
    Abstract: A conductive interconnect structure includes a contact pad; a conductive body connected to the contact pad at a first end; and a conductive layer positioned on a second end of the conductive body. The conductive body has a longitudinal direction perpendicular to a surface of the contact pad. The conductive body has an average grain size (a) on a cross sectional plane (Plane A) whose normal is perpendicular to the longitudinal direction of the conductive body. The conductive layer has an average grain size (b) on Plane A. The conductive body and the conductive layer are composed of same material, and the average grain size (a) is greater than the average grain size (b).
    Type: Application
    Filed: March 28, 2016
    Publication date: July 21, 2016
    Inventors: MENG-TSE CHEN, HSIU-JEN LIN, CHIH-WEI LIN, MING-DA CHENG, CHIH-HANG TUNG, CHUNG-SHI LIU