Patents by Inventor Chih-Hang Tung

Chih-Hang Tung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120125981
    Abstract: A method includes heating a package structure including a first work piece and a second work piece to melt a plurality of solder bumps between the first and the second work pieces; and after the step of heating, allowing the plurality of solder bumps to solidify. During the step of solidifying, a first side of the package structure is maintained at a first temperature higher than a melting temperature of the plurality of solder bumps by using a heating source. During the step of solidifying, a second side of the package structure is maintained at a second temperature lower than the melting temperature by using a cooling source, wherein the second side is opposite the first side.
    Type: Application
    Filed: November 24, 2010
    Publication date: May 24, 2012
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Horng Chang, Yian-Liang Kuo, Chih-Hang Tung, Tsung-Fu Tsai
  • Publication number: 20120063090
    Abstract: An apparatus for cooling a stacked die package comprises a substrate, a first die above the substrate, a second die above the first die, and a housing containing the first and second dies. The housing seals the first and second dies from the environment. The apparatus further includes a cooling fluid in fluid communication with the first die and the second die to transfer the heat from the dies to the housing.
    Type: Application
    Filed: September 9, 2010
    Publication date: March 15, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Li HSIAO, Chen-Hua YU, Da-Yuan SHIH, Chih-Hang TUNG, Chun Hui YU
  • Publication number: 20120061059
    Abstract: An apparatus for cooling a stacked die package comprises a first die provided above a substrate; a second die above the first die; a cooling fluid in fluid communication with the first die and the second die, the cooling fluid for absorbing thermal energy from the first and the second die; a housing containing the first and second dies, the housing sealing the first and second dies from an environment, wherein the housing further includes a first opening and a second opening, the first and second openings being vertically displaced from one another; a conduit having one end connected to the first opening and the other end connected to the second opening, the conduit allowing the cooling liquid to circulate from the first opening to the second opening; a first temperature sensor being arranged to provide an output that is dependent on a local temperature at the first opening; and a second temperature sensor being arranged to provide an output that is dependent on a local temperature at the second opening, wher
    Type: Application
    Filed: February 24, 2011
    Publication date: March 15, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Li HSIAO, Chen-Hua Yu, Da-Yuan Shih, Chih-Hang Tung, Chun Hui Yu
  • Publication number: 20110186989
    Abstract: A semiconductor device includes a solder bump overlying and electrically connected to a pad region, and a metal cap layer formed on at least a portion of the solder bump. The metal cap layer has a melting temperature greater than the melting temperature of the solder bump.
    Type: Application
    Filed: September 16, 2010
    Publication date: August 4, 2011
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Li Hsiao, Chen-Hua Yu, Shin-Puu Jeng, Chih-Hang Tung, Cheng-Chang Wei
  • Publication number: 20100276761
    Abstract: Non-planar transistors and methods of fabrication thereof are described. In an embodiment, a method of forming a non-planar transistor includes forming a channel region on a first portion of a semiconductor fin, the semiconductor fin having a top surface and sidewalls. A gate electrode is formed over the channel region of the semiconductor fin, and an in-situ doped semiconductor layer is grown on the top surface and the sidewalls of the semiconductor fin on opposing sides of the gate electrode using a selective epitaxial growth process. At least a part of the doped semiconductor layer is converted to form a dopant rich region.
    Type: Application
    Filed: January 6, 2010
    Publication date: November 4, 2010
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hang Tung, Chin-Hsiang Lin, Cheng-Hung Chang, Sey-Ping Sun