Abstract: Semiconductor structures and methods of forming the same are provided. A semiconductor structure according to one embodiment includes first nanostructures, a first gate structure wrapping around each of the first nanostructures and disposed over an isolation structure, and a backside gate contact disposed below the first nanostructures and adjacent to the isolation structure. A bottom surface of the first gate structure is in direct contact with the backside gate contact.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a gate stack and a contact over a fin structure, a gate spacer layer between the gate stack and the contact, a first mask layer over the gate stack, and a second mask layer over the contact. The first mask layer includes a protruding portion sandwiched between an upper portion of the second mask layer and the gate spacer layer.

Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package includes a molded semiconductor device, a first redistribution structure, and conductive vias. The molded semiconductor device comprises a sensor die with a first surface and a second surface opposite the first surface, wherein the sensor die has an input/output region and a sensing region at the first surface. The first redistribution structure is disposed on the first surface of the sensor die, wherein the first redistribution structure covers the input/output region and exposes the sensing region, and the first redistribution structure comprises a conductive layer having a redistribution pattern and a ring structure. The redistribution pattern is electrically connected with the sensor die. The ring structure surrounds the sensing region and is separated from the redistribution pattern, wherein the ring structure is closer to the sensing region than the redistribution pattern.

Abstract: A fan assembly includes a socket to receive a fan module, a fan flap coupled to a first side wall of the socket, and an anti-reflow device coupled to a second side wall of the socket. The fan flap moves in a curved path between a first position and a second position. The anti-reflow device has an attachment feature, an embossed feature, and a stopping feature. The attachment feature attaches the anti-reflow device to the second side wall. The embossed feature extends through a first aperture in the second side wall. The stopping feature extends through a second aperture in the second side wall and contacts the fan flap. When the fan module is removed, the stopping feature retains the fan flap in the first position to block the socket and prevent air from reflowing through the socket.

Abstract: Semiconductor devices and manufacturing and design methods thereof are disclosed. In one embodiment, a semiconductor device includes an active FinFET disposed over a workpiece comprising a first semiconductive material, the active FinFET comprising a first fin. An electrically inactive FinFET structure is disposed over the workpiece proximate the active FinFET, the electrically inactive FinFET comprising a second fin. A second semiconductive material is disposed between the first fin and the second fin.

Abstract: A video encoding method includes: during a first period, performing an encoding process upon a first block group of a current frame to generate a first block group bitstream; and during a second period, transmitting a second block group bitstream derived from encoding a second block group of the current frame, wherein the second period overlaps the first period. The encoding process includes: during a first time segment of the first period, performing a first in-loop filtering process upon a first group of pixels; and during a second time segment of the first period, performing a second in-loop filtering process upon a second group of pixels, wherein the second time segment overlaps the first time segment, and a non-zero pixel distance exists between a first edge pixel of the first group of pixels and a second edge pixel of the second group of pixels in a filter direction.

Abstract: A semiconductor device includes a first fin field effect transistor (FinFET) and a contact bar (source/drain (S/D) contact layer). The first FinFET includes a first fin structure extending in a first direction, a first gate structure extending in a second direction crossing the first direction, and a first S/D structure. The contact bar is disposed over the first S/D structure and extends in the second direction crossing the first S/D structure in plan view. The contact bar includes a first portion disposed over the first S/D structure and a second portion. The second portion overlaps no fin structure and no S/D structure. A width of the second portion in the first direction is smaller than a width of the first portion in the first direction in plan view.

Abstract: A circuit substrate includes a base substrate, a plurality of conductive vias, a first redistribution circuit structure, a second redistribution circuit structure and a semiconductor die. The plurality of conductive vias penetrate through the base substrate. The first redistribution circuit structure is located on the base substrate and connected to the plurality of conductive vias. The second redistribution circuit structure is located over the base substrate and electrically connected to the plurality of conductive vias, where the second redistribution circuit structure includes a plurality of conductive blocks, and at least one of the plurality of conductive blocks is electrically connected to two or more than two of the plurality of conductive vias, and where the base substrate is located between the first redistribution circuit structure and the second redistribution circuit structure.

Abstract: A method for microstructure modification of conducting lines is provided. An electroplating process is performed to deposit the metal thin film/conducting line(s) with a face-centered cubic (FCC) structure and a preferred crystallographic orientation over a surface of a substrate. The metal thin film/ conducting line(s) is subsequently subjected to a thermal annealing process to modify its microstructure with the grain sizes in a range of 5 ?m to 100 ?m. The thermal annealing process is conducted at the temperature of above 25 degrees Celsius and below 240 degrees Celsius.

Abstract: A semiconductor package is provided. The semiconductor package includes a heat dissipation substrate including a first conductive through-via embedded therein; a sensor die disposed on the heat dissipation substrate; an insulating encapsulant laterally encapsulating the sensor die; a second conductive through-via penetrating through the insulating encapsulant; and a first redistribution structure and a second redistribution structure disposed on opposite sides of the heat dissipation substrate. The second conductive through-via is in contact with the first conductive through-via. The sensor die is located between the second redistribution structure and the heat dissipation substrate. The second redistribution structure has a window allowing a sensing region of the sensor die receiving light. The first redistribution structure is electrically connected to the sensor die through the first conductive through-via, the second conductive through-via and the second redistribution structure.

Abstract: A method for microstructure modification of conducting lines is provided. An electroplating process is performed to deposit the metal thin film/conducting line(s) with a face-centered cubic (FCC) structure and a preferred crystallographic orientation over a surface of a substrate. The metal thin film/conducting line(s) is subsequently subjected to a thermal annealing process to modify its microstructure with the grain sizes in a range of 5 ?m to 100 ?m. The thermal annealing process is conducted at the temperature of above 25 degrees Celsius and below 240 degrees Celsius.

Abstract: A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy, gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region.

Abstract: A removable lever apparatus for inserting and removing computer equipment from a chassis module of a server rack includes a central rotatable structure, a long arm connected to and extending in a first direction away from the central rotatable structure, and a short arm connected to and extending in a second direction away from the central rotatable structure. The central rotatable structure includes a rotation stopper for limiting rotation about the axis of rotation between an inserting position and a removing position. The central rotatable structure also includes a retention structure for maintaining the coupling to the tray when the central rotatable structure is in a position other than the inserting position. The short arm is configured to engage a side wall of the chassis module when the central rotatable structure is rotated.

Abstract: A semiconductor package is provided. The semiconductor package includes a heat dissipation substrate including a first conductive through-via embedded therein; a sensor die disposed on the heat dissipation substrate; an insulating encapsulant laterally encapsulating the sensor die; a second conductive through-via penetrating through the insulating encapsulant; and a first redistribution structure and a second redistribution structure disposed on opposite sides of the heat dissipation substrate. The second conductive through-via is in contact with the first conductive through-via. The sensor die is located between the second redistribution structure and the heat dissipation substrate. The second redistribution structure has a window allowing a sensing region of the sensor die receiving light. The first redistribution structure is electrically connected to the sensor die through the first conductive through-via, the second conductive through-via and the second redistribution structure.

Abstract: A component housing insertable in a chassis for a computing device blocking air flow when in a pulled out position is disclosed. The component housing has a front end and an opposite rear end. A pair of side walls are provided between the front end and the rear end. The side walls are slidably connected to the chassis to allow the component housing to be moved between an inserted position and the pulled-out position. A cover on the rear end has an open position allowing air flow through the rear end when the component housing is in the inserted position. The cover has a closed position blocking air flow through the aperture when the component housing is in the pulled out position.

Abstract: A field effect transistor includes a substrate comprising a fin structure. The field effect transistor further includes an isolation structure in the substrate. The field effect transistor further includes a source/drain (S/D) recess cavity below a top surface of the substrate. The S/D recess cavity is between the fin structure and the isolation structure. The field effect transistor further includes a strained structure in the S/D recess cavity. The strain structure includes a lower portion. The lower portion includes a first strained layer, wherein the first strained layer is in direct contact with the isolation structure, and a dielectric layer, wherein the dielectric layer is in direct contact with the substrate, and the first strained layer is in direct contact with the dielectric layer. The strained structure further includes an upper portion comprising a second strained layer overlying the first strained layer.

Abstract: A removable lever apparatus for inserting and removing computer equipment from a chassis module of a server rack includes a central rotatable structure, a long arm connected to and extending in a first direction away from the central rotatable structure, and a short arm connected to and extending in a second direction away from the central rotatable structure. The central rotatable structure includes a rotation stopper for limiting rotation about the axis of rotation between an inserting position and a removing position. The central rotatable structure also includes a retention structure for maintaining the coupling to the tray when the central rotatable structure is in a position other than the inserting position. The short arm is configured to engage a side wall of the chassis module when the central rotatable structure is rotated.

Abstract: A semiconductor package includes a first chip and a second chip arranged side by side on a carrier substrate. The first chip is provided with a high-speed signal pads along a first side in proximity to the second chip. The second chip includes a redistribution layer, and the redistribution layer is provided with data (DQ) pads along the second side in proximity to the first chip. A plurality of first bonding wires is provided to directly connect the high-speed signal pads to the DQ pads. The redistribution layer of the second chip is provided with first command/address (CA) pads along the third side opposite to the second side, and a plurality of dummy pads corresponding to the first CA pads. The plurality of dummy pads are connected to second CA pads disposed along a fourth side of the second chip via interconnects of the redistribution layer.

Abstract: An implant guide system for hip replacement surgery includes an angle guide member and a first positioning plate. The angle guide member has a body and a protrusion that are substantially connected to each other. The body has a curved surface corresponding in shape to a surface of a patient's acetabulum. The protrusion has a first through hole extending to the body. An acute angle is defined between an extension line of the first through hole and a flat surface of the body. The first positioning plate has a first holding portion and a first spacing portion that are substantially connected to each other. The first spacing portion has a second through hole, a third through hole and a fourth through hole that are parallel to each other.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a source/drain contact structure formed over a semiconductor substrate, and a first gate stack formed over the semiconductor substrate and adjacent to the source/drain contact structure. The semiconductor device structure also includes an insulating cap structure formed over and separated from an upper surface of the first gate stack. In addition, the semiconductor device structure includes first gate spacers formed over opposing sidewalls of the first gate stack to separate the first gate stack from the source/drain contact structure. The first gate spacers extend over opposing sidewalls of the insulating cap structure, so as to form an air gap surrounded by the first gate spacers, the first gate stack, and the insulating cap structure.