Patents by Inventor Chih-Hao Chang

Chih-Hao Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210225766
    Abstract: A semiconductor structure includes a metal gate structure disposed over a semiconductor substrate, a gate spacer disposed on a sidewall of the metal gate structure, an source/drain contact disposed over the semiconductor substrate and separated from the metal gate structure by the gate spacer, and a contact feature coupling the metal gate structure to the source/drain contact. The contact feature may be configured to include a dielectric layer disposed on a metal layer, where the dielectric layer and the metal layer are defined by continuous sidewalls.
    Type: Application
    Filed: January 17, 2020
    Publication date: July 22, 2021
    Inventors: Jia-Chuan You, Chia-Hao Chang, Tien-Lu Lin, Yu-Ming Lin, Chih-Hao Wang
  • Publication number: 20210225697
    Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a first conductive structure over the semiconductor substrate. The semiconductor device structure also includes a first dielectric layer surrounding the first conductive structure and a second dielectric layer over the first dielectric layer. The semiconductor device structure further includes a second conductive structure partially surrounded by the second dielectric layer and partially surrounded by the first conductive structure. In addition, the semiconductor device structure includes an interfacial layer separating the first conductive structure from the second conductive structure.
    Type: Application
    Filed: January 16, 2020
    Publication date: July 22, 2021
    Inventors: Chun-Yuan CHEN, Chia-Hao CHANG, Cheng-Chi CHUANG, Yu-Ming LIN, Chih-Hao WANG
  • Patent number: 11069811
    Abstract: A method for forming a semiconductor device structure is provided. The method for forming the semiconductor device structure includes forming a first mask layer covering the gate stack, forming a contact alongside the gate stack and the first mask layer, recessing the contact, etching the first mask layer, and forming a second mask layer covering the contact and a portion of the first mask layer.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: July 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Lin-Yu Huang, Jia-Chuan You, Chia-Hao Chang, Tien-Lu Lin, Yu-Ming Lin, Chih-Hao Wang
  • Publication number: 20210217757
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a source/drain structure, a metal gate structure, a ferroelectric layer, a spacer and a metal layer. The source/drain structure is disposed over the substrate. The metal gate structure is disposed over the substrate and between the source/drain structure. The ferroelectric layer is disposed over the metal gate structure and the source/drain structure. The spacer is disposed over the ferroelectric layer. The metal layer is disposed over the ferroelectric layer and surrounded by the spacer. A method for manufacturing a semiconductor structure is also provided.
    Type: Application
    Filed: January 9, 2020
    Publication date: July 15, 2021
    Inventors: CHIH-YU CHANG, SAI-HOOI YEONG, YU-MING LIN, CHIH-HAO WANG
  • Publication number: 20210217847
    Abstract: The present disclosure provides a semiconductor structure, including a substrate having a memory region and a logic region, the memory region including a first group of nanosheets vertically arranged over a first region of the substrate, wherein the first group of nanosheets includes: a first semiconductor nanosheet, a second group of nanosheets vertically arranged over a second region of the substrate adjacent to the first region, wherein the second group of nanosheets includes: a second semiconductor nanosheet, and a third semiconductor nanosheet over the second semiconductor nanosheet, a first metal gate layer surrounding the first semiconductor nanosheet, and a second metal gate layer surrounding the second semiconductor nanosheet, wherein the first metal gate layer is in direct contact with the second metal gate layer.
    Type: Application
    Filed: January 10, 2020
    Publication date: July 15, 2021
    Inventors: CHIH-YU CHANG, SAI-HOOI YEONG, YU-MING LIN, CHIH-HAO WANG
  • Patent number: 11018242
    Abstract: A method includes forming a fin extending above an isolation region. A sacrificial gate stack having a first sidewall and a second sidewall opposite the first sidewall is formed over the fin. A first spacer is formed on the first sidewall of the sacrificial gate stack. A second spacer is formed on the second sidewall of the sacrificial gate stack. A patterned mask having an opening therein is formed over the sacrificial gate stack, the first spacer and the second spacer. The patterned mask extends along a top surface and a sidewall of the first spacer. The second spacer is exposed through the opening in the patterned mask. The fin is patterned using the patterned mask, the sacrificial gate stack, the first spacer and the second spacer as a combined mask to form a recess in the fin. A source/drain region is epitaxially grown in the recess.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: May 25, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ting Li, Bi-Fen Wu, Jen-Hsiang Lu, Chih-Hao Chang
  • Patent number: 10998442
    Abstract: A field effect transistor includes a substrate comprising a fin structure. The field effect transistor further includes an isolation structure in the substrate. The field effect transistor further includes a source/drain (S/D) recess cavity below a top surface of the substrate. The S/D recess cavity is between the fin structure and the isolation structure. The field effect transistor further includes a strained structure in the S/D recess cavity. The strain structure includes a lower portion. The lower portion includes a first strained layer, wherein the first strained layer is in direct contact with the isolation structure, and a dielectric layer, wherein the dielectric layer is in direct contact with the substrate, and the first strained layer is in direct contact with the dielectric layer. The strained structure further includes an upper portion comprising a second strained layer overlying the first strained layer.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: May 4, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Lin Lee, Chih-Hao Chang, Chih-Hsin Ko, Feng Yuan, Jeff J. Xu
  • Publication number: 20210118846
    Abstract: A semiconductor package includes a carrier substrate including opposite first surface and second surface; a first chip and a second chip mounted on the first surface of the carrier substrate in a side-by-side manner, wherein the first chip has a plurality of high-speed signal pads disposed along its first side adjacent to the second chip, and the second chip has a plurality of data (DQ) pads along its second side adjacent to the first chip; and a plurality of first bonding wires, directly connecting the plurality of high-speed signal pads to the plurality of data (DQ) pads.
    Type: Application
    Filed: May 12, 2020
    Publication date: April 22, 2021
    Inventors: Chin-Yuan Lo, Nan-Chin Chuang, Chih-Hao Chang
  • Publication number: 20210114021
    Abstract: Various examples are provided related to surfaces that can achieve controllable dynamic iridescence. In one example, a magnetically actuated surface includes an array of magnetic nanopillars; and a ferrofluid sealed in a microfluidic channel over the array of magnetic nanopillars. In another example, a method for forming a magnetically actuated surface includes generating a 2D periodic array of recesses in a photoresist layer; generating a nanopillar template from the 2D periodic array of recesses in the photoresist layer; forming a microfluidic channel over the nanopillar template; and filling the microfluidic channel with a ferrofluid comprising magnetic nanoparticles in a fluid medium.
    Type: Application
    Filed: October 19, 2020
    Publication date: April 22, 2021
    Inventors: Chih-Hao Chang, Zhiren Luo
  • Patent number: 10966595
    Abstract: An endoscopy auxiliary device includes an insertion tube and a clamping unit. The clamping unit has a pipe and a connector. The connector is connected to the insertion tube. The tube is configured to clamp a capsule endoscope. The pipe has an inner space configured to accommodate a part of the capsule endoscope. The pipe includes a first slit, a second slit and a third slit. The first slit extends from a free end of the pipe for a first distance toward a connection end of the pipe. The second slit extends from the free end of the pipe for the connection distance toward the connection end of the pipe. The third slit extends from the free end of the pipe for a third distance toward the connection end of the pipe. The first slit, the second slit and the third slit are separate.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: April 6, 2021
    Assignee: INSIGHT MEDICAL SOLUTIONS INC.
    Inventors: Yu-Jen Wu, Ching-Lung Kuo, Chih-Hao Chang, Ping-Chun Tsai, Shih-Chieh Lu
  • Publication number: 20210098636
    Abstract: A semiconductor package is provided. The semiconductor package includes a heat dissipation substrate including a first conductive through-via embedded therein; a sensor die disposed on the heat dissipation substrate; an insulating encapsulant laterally encapsulating the sensor die; a second conductive through-via penetrating through the insulating encapsulant; and a first redistribution structure and a second redistribution structure disposed on opposite sides of the heat dissipation substrate. The second conductive through-via is in contact with the first conductive through-via. The sensor die is located between the second redistribution structure and the heat dissipation substrate. The second redistribution structure has a window allowing a sensing region of the sensor die receiving light. The first redistribution structure is electrically connected to the sensor die through the first conductive through-via, the second conductive through-via and the second redistribution structure.
    Type: Application
    Filed: January 20, 2020
    Publication date: April 1, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Yu-Chih Huang, Chih-Hao Chang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
  • Publication number: 20210098452
    Abstract: Semiconductor devices and manufacturing and design methods thereof are disclosed. In one embodiment, a semiconductor device includes an active FinFET disposed over a workpiece comprising a first semiconductive material, the active FinFET comprising a first fin. An electrically inactive FinFET structure is disposed over the workpiece proximate the active FinFET, the electrically inactive FinFET comprising a second fin. A second semiconductive material is disposed between the first fin and the second fin.
    Type: Application
    Filed: December 14, 2020
    Publication date: April 1, 2021
    Inventors: Tung Ying Lee, Wen-Huei Guo, Chih-Hao Chang, Shou-Zen Chang
  • Publication number: 20210083046
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a source/drain contact structure formed over a semiconductor substrate, and a first gate stack formed over the semiconductor substrate and adjacent to the source/drain contact structure. The semiconductor device structure also includes an insulating cap structure formed over and separated from an upper surface of the first gate stack. In addition, the semiconductor device structure includes first gate spacers formed over opposing sidewalls of the first gate stack to separate the first gate stack from the source/drain contact structure. The first gate spacers extend over opposing sidewalls of the insulating cap structure, so as to form an air gap surrounded by the first gate spacers, the first gate stack, and the insulating cap structure.
    Type: Application
    Filed: September 16, 2019
    Publication date: March 18, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tien-Lu LIN, Che-Chen WU, Chia-Lin CHUANG, Yu-Ming LIN, Chih-Hao CHANG
  • Patent number: 10939945
    Abstract: A minimally invasive bone fracture positioning device includes a sleeve, a movable unit, and a support. The sleeve includes an alignment portion located on a longitudinal axis of the sleeve. The movable unit includes a positioning portion. The positioning portion is located on the longitudinal axis and is spaced from the alignment portion. The movable unit is mounted in a radial direction of the sleeve. The movable unit is slideable relative to the sleeve along the longitudinal axis. A support is coupled to the sleeve and the movable unit. The movable unit is spaced from the sleeve by the support.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: March 9, 2021
    Assignee: METAL INDUSTRIES RESEARCH & DEVELOPMENT CENTRE
    Inventors: Yue-Jun Wang, Chih-Hao Chang, Shih-Hua Huang, Chih-Lung Lin, Tung-Lin Tsai, Chun-Chieh Tseng, Li-Wen Weng
  • Patent number: 10939579
    Abstract: A fan guard connector is provided. The fan guard connector includes a fan guard structure configured to be secured to a cooling system. The fan guard connector also includes a lever structure connected to the fan guard structure by a pivot element. The lever structure is configured to rotate between an engaged and a disengaged position. The fan guard connector also includes a connector member configured to secure the lever structure to the fan guard structure in the engaged position.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: March 2, 2021
    Assignee: QUANTA COMPUTER INC.
    Inventors: Yaw-Tzorng Tsorng, Chun Chang, Cheng-Chieh Weng, Chih-Hao Chang
  • Publication number: 20200403085
    Abstract: A method includes forming a fin extending above an isolation region. A sacrificial gate stack having a first sidewall and a second sidewall opposite the first sidewall is formed over the fin. A first spacer is formed on the first sidewall of the sacrificial gate stack. A second spacer is formed on the second sidewall of the sacrificial gate stack. A patterned mask having an opening therein is formed over the sacrificial gate stack, the first spacer and the second spacer. The patterned mask extends along a top surface and a sidewall of the first spacer. The second spacer is exposed through the opening in the patterned mask. The fin is patterned using the patterned mask, the sacrificial gate stack, the first spacer and the second spacer as a combined mask to form a recess in the fin. A source/drain region is epitaxially grown in the recess.
    Type: Application
    Filed: September 3, 2020
    Publication date: December 24, 2020
    Inventors: Chung-Ting Li, Bi-Fen Wu, Jen-Hsiang Lu, Chih-Hao Chang
  • Patent number: 10868004
    Abstract: Semiconductor devices and manufacturing and design methods thereof are disclosed. In one embodiment, a semiconductor device includes an active FinFET disposed over a workpiece comprising a first semiconductive material, the active FinFET comprising a first fin. An electrically inactive FinFET structure is disposed over the workpiece proximate the active FinFET, the electrically inactive FinFET comprising a second fin. A second semiconductive material is disposed between the first fin and the second fin.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tung Ying Lee, Wen-Huei Guo, Chih-Hao Chang, Shou-Zen Chang
  • Publication number: 20200381428
    Abstract: A semiconductor device includes a first fin field effect transistor (FinFET) and a contact bar (source/drain (S/D) contact layer). The first FinFET includes a first fin structure extending in a first direction, a first gate structure extending in a second direction crossing the first direction, and a first S/D structure. The contact bar is disposed over the first S/D structure and extends in the second direction crossing the first S/D structure in plan view. The contact bar includes a first portion disposed over the first S/D structure and a second portion. The second portion overlaps no fin structure and no S/D structure. A width of the second portion in the first direction is smaller than a width of the first portion in the first direction in plan view.
    Type: Application
    Filed: August 17, 2020
    Publication date: December 3, 2020
    Inventors: Chih-Hao CHANG, Wen-Huei GUO, Yi-Shien MOR
  • Publication number: 20200365697
    Abstract: A method of forming a semiconductor device includes forming a gate structure on a semiconductor substrate. A gate spacer is formed adjacent to the gate structure. The gate spacer includes a first dielectric layer and a second dielectric layer on the first dielectric layer. A plasma treatment is performed to the second dielectric layer. After performing the plasma treatment, at least a portion of the second dielectric layer is removed such that a sidewall of the first dielectric layer is exposed. A dielectric cap is formed on the gate spacer.
    Type: Application
    Filed: August 7, 2020
    Publication date: November 19, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Ting LI, Jen-Hsiang LU, Chih-Hao CHANG
  • Publication number: 20200365736
    Abstract: A field effect transistor includes a substrate comprising a fin structure. The field effect transistor further includes an isolation structure in the substrate. The field effect transistor further includes a source/drain (S/D) recess cavity below a top surface of the substrate. The S/D recess cavity is between the fin structure and the isolation structure. The field effect transistor further includes a strained structure in the S/D recess cavity. The strain structure includes a lower portion. The lower portion includes a first strained layer, wherein the first strained layer is in direct contact with the isolation structure, and a dielectric layer, wherein the dielectric layer is in direct contact with the substrate, and the first strained layer is in direct contact with the dielectric layer. The strained structure further includes an upper portion comprising a second strained layer overlying the first strained layer.
    Type: Application
    Filed: August 5, 2020
    Publication date: November 19, 2020
    Inventors: Tsung-Lin Lee, Chih-Hao Chang, Chih-Hsin Ko, Feng Yuan, Jeff J. Xu