Abstract: A fan assembly includes a socket to receive a fan module, a fan flap coupled to a first side wall of the socket, and an anti-reflow device coupled to a second side wall of the socket. The fan flap moves in a curved path between a first position and a second position. The anti-reflow device has an attachment feature, an embossed feature, and a stopping feature. The attachment feature attaches the anti-reflow device to the second side wall. The embossed feature extends through a first aperture in the second side wall. The stopping feature extends through a second aperture in the second side wall and contacts the fan flap. When the fan module is removed, the stopping feature retains the fan flap in the first position to block the socket and prevent air from reflowing through the socket.

Abstract: A touch display device including a first substrate, a second substrate, a display medium, and a pixel array structure is provided. The pixel array structure includes a scan line, a data line, an active device, pixel electrodes, a signal electrode layer and a signal transmission layer. The scan line intersects the data line. The active device is connected to the scan line and the data line. The pixel electrodes are arranged in an array. The signal electrode layer includes signal electrodes. The signal transmission layer includes a signal line disposed between two adjacent columns of the pixel electrodes and electrically connected to one of the signal electrodes. The data line includes at least a portion located outside of the signal line.

Abstract: A semiconductor device includes a first fin field effect transistor (FinFET) and a contact bar (source/drain (S/D) contact layer). The first FinFET includes a first fin structure extending in a first direction, a first gate structure extending in a second direction crossing the first direction, and a first S/D structure. The contact bar is disposed over the first S/D structure and extends in the second direction crossing the first S/D structure in plan view. The contact bar includes a first portion disposed over the first S/D structure and a second portion. The second portion overlaps no fin structure and no S/D structure. A width of the second portion in the first direction is smaller than a width of the first portion in the first direction in plan view.

Abstract: A semiconductor device includes a semiconductor substrate, at least one gate stack, a gate spacer and a dielectric cap. The gate stack is located on the semiconductor substrate. The gate spacer is located on a sidewall of the gate stack. The gate spacer includes a first dielectric layer and a second dielectric layer with different etch properties. The dielectric cap at least caps the gate spacer. The dielectric cap and the second dielectric layer define a gap therebetween.

Abstract: A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region.

Abstract: A package structure and a method of manufacturing the same are provided. The package structure includes a die, a RDL structure, an encapsulant and a conductive terminal. The die is on a redistribution layer (RDL) structure. The RDL structure comprises a polymer layer and a RDL in the polymer layer. The encapsulant is on the RDL structure and laterally aside the die. The encapsulant comprises a body part and an extending part underlying the body part. The conductive terminal is electrically connected to the RDL structure and the die. The body part of the encapsulant encapsulates sidewalls of the die. The extending part of the encapsulant extends into the polymer layer.

Abstract: In a method of manufacturing a semiconductor device, a first fin structure for an n-channel fin field effect transistor (FinFET) is formed over a substrate. An isolation insulating layer is formed over the substrate such that an upper portion of the first fin structure protrudes from the isolation insulating layer. A gate structure is formed over a part of the upper portion of the first fin structure. A first source/drain (S/D) epitaxial layer is formed over the first fin structure not covered by the gate structure. A cap epitaxial layer is formed over the first S/D epitaxial layer. The first S/D epitaxial layer includes SiP, and the cap epitaxial layer includes SiC with a carbon concentration is in a range from 0.5 atomic % to 5 atomic %.

Abstract: An embodiment of a method for forming a transistor that includes providing a semiconductor substrate having a source/drain region is provided where a first SiGe layer is formed over the source/drain region. A thermal oxidation is performed to convert a top portion of the first SiGe layer to an oxide layer and a bottom portion of the first SiGe layer to a second SiGe layer. A thermal diffusion process is performed after the thermal oxidation is performed to form a SiGe area from the second SiGe layer. The SiGe area has a higher Ge concentration than the first SiGe layer.

Abstract: A system and method for detecting and compensating for temperature effects in a device having a power supply and a remote node. The system includes a power supply unit having an adjustable voltage output and a feedback circuit. The voltage output is adjusted based on the output of the feedback circuit. A power path is coupled to the power supply unit. The power path has power connectors to supply voltage from the power supply unit to a remote node. The remote node is operable to sense a voltage drop of the power path at the remote node associated with temperature effects on the power connectors. An adjustable resistor has an output coupled to the feedback circuit. A controller is coupled to the remote node and the adjustable resistor. The controller determines a resistance value to compensate for the temperature effects and sets the adjustable resistor to change the power output.

Abstract: A method includes forming a fin extending above an isolation region. A sacrificial gate stack having a first sidewall and a second sidewall opposite the first sidewall is formed over the fin. A first spacer is formed on the first sidewall of the sacrificial gate stack. A second spacer is formed on the second sidewall of the sacrificial gate stack. A patterned mask having an opening therein is formed over the sacrificial gate stack, the first spacer and the second spacer. The patterned mask extends along a top surface and a sidewall of the first spacer. The second spacer is exposed through the opening in the patterned mask. The fin is patterned using the patterned mask, the sacrificial gate stack, the first spacer and the second spacer as a combined mask to form a recess in the fin. A source/drain region is epitaxially grown in the recess.

Abstract: A field effect transistor includes a substrate comprising a fin structure. The field effect transistor further includes an isolation structure in the substrate. The field effect transistor further includes a source/drain (S/D) recess cavity below a top surface of the substrate. The S/D recess cavity is between the fin structure and the isolation structure. The field effect transistor further includes a strained structure in the S/D recess cavity. The strain structure includes a lower portion. The lower portion includes a first strained layer, wherein the first strained layer is in direct contact with the isolation structure, and a dielectric layer, wherein the dielectric layer is in direct contact with the substrate, and the first strained layer is in direct contact with the dielectric layer. The strained structure further includes an upper portion comprising a second strained layer overlying the first strained layer.

Abstract: Semiconductor devices and manufacturing and design methods thereof are disclosed. In one embodiment, a semiconductor device includes an active FinFET disposed over a workpiece comprising a first semiconductive material, the active FinFET comprising a first fin. An electrically inactive FinFET structure is disposed over the workpiece proximate the active FinFET, the electrically inactive FinFET comprising a second fin. A second semiconductive material is disposed between the first fin and the second fin.

Abstract: Methods for fabricating FinFETs with enhanced performance are disclosed herein. An exemplary method includes forming a first fin and a second fin having a trench defined therebetween. The first fin and the second fin each include a first semiconductor layer disposed over a second semiconductor layer. An isolation feature is formed in the trench between the first fin and the second fin. A gate structure is formed over the isolation feature, a first region of the first fin, and a first region of the second fin. The gate structure is disposed between second regions of the first fin and between second regions of the second fin. After recessing the first fin and the second fin, a third semiconductor layer is formed over the first fin and the second fin. In some embodiments, the third semiconductor layer extends over the isolation feature and merges the first fin and the second fin.

Abstract: A fan guard connector is provided. The fan guard connector includes a fan guard structure configured to be secured to a cooling system. The fan guard connector also includes a lever structure connected to the fan guard structure by a pivot element. The lever structure is configured to rotate between an engaged and a disengaged position. The fan guard connector also includes a connector member configured to secure the lever structure to the fan guard structure in the engaged position.

Abstract: A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region.

Abstract: A display brightness adjusting method includes detecting a brightness of individual pixel regions of a display apparatus to acquire grayscale values. The brightness distribution information is analyzed to acquire a first compensation value to be applied to each pixel region and a first gamma voltage based on the first compensation value is calculated and applied. The uniformity of brightness of each pixel region is improved.

Abstract: A display brightness adjusting method includes detecting a brightness of individual pixel regions of a display apparatus to acquire grayscale values. The brightness distribution information is analyzed to acquire a first compensation value to be applied to each pixel region and a first gamma voltage based on the first compensation value is calculated and applied. The uniformity of brightness of each pixel region is improved.

Abstract: A method includes forming a fin extending above an isolation region. A sacrificial gate stack having a first sidewall and a second sidewall opposite the first sidewall is formed over the fin. A first spacer is formed on the first sidewall of the sacrificial gate stack. A second spacer is formed on the second sidewall of the sacrificial gate stack. A patterned mask having an opening therein is formed over the sacrificial gate stack, the first spacer and the second spacer. The patterned mask extends along a top surface and a sidewall of the first spacer. The second spacer is exposed through the opening in the patterned mask. The fin is patterned using the patterned mask, the sacrificial gate stack, the first spacer and the second spacer as a combined mask to form a recess in the fin. A source/drain region is epitaxially grown in the recess.

Abstract: Semiconductor devices and manufacturing and design methods thereof are disclosed. In one embodiment, a semiconductor device includes an active FinFET disposed over a workpiece comprising a first semiconductive material, the active FinFET comprising a first fin. An electrically inactive FinFET structure is disposed over the workpiece proximate the active FinFET, the electrically inactive FinFET comprising a second fin. A second semiconductive material is disposed between the first fin and the second fin.

Abstract: The present disclosure provides a system and method for enabling cableless connections within a server system. The server system comprises a motherboard (MB) module, a power distribution board (PDB) module, power supply unit (PSU) modules, network interface controller (NIC) modules, fan modules, graphic process unit (GPU) modules, and a hyperscale GPU accelerator (HGX) platform. These components of the server system are interconnected by a plurality of circuit boards. The plurality of circuit boards includes, but is not limited to, a main board, linking boards (BDs), a PDB, a fan board, a power linking board, peripheral-component-interconnect-express (PCIe) expander boards, a plurality of NVLink bridges, and HGX base boards.