Patents by Inventor Chih-Hao Chiang

Chih-Hao Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240071954
    Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.
    Type: Application
    Filed: November 9, 2023
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Ming Chiang, Chao-wei Li, Wei-Lun Tsai, Chia-Min Lin, Yi-Da Tsai, Sheng-Feng Weng, Yu-Hao Chen, Sheng-Hsiang Chiu, Chih-Wei Lin, Ching-Hua Hsieh
  • Publication number: 20240071953
    Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above- mentioned memory device is also provided.
    Type: Application
    Filed: November 6, 2023
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Ming Chiang, Chao-wei Li, Wei-Lun Tsai, Chia-Min Lin, Yi-Da Tsai, Sheng-Feng Weng, Yu-Hao Chen, Sheng-Hsiang Chiu, Chih-Wei Lin, Ching-Hua Hsieh
  • Publication number: 20240072147
    Abstract: A semiconductor device includes a substrate, a shallow trench isolation structure, two epitaxial structures, one or more semiconductor channel layers, a gate metal layer and a gate spacer. The shallow trench isolation structure is disposed over the substrate. The epitaxial structures are disposed over the shallow trench isolation structure. The one or more semiconductor channel layers connect the two epitaxial structures. The gate metal layer is located between the epitaxial structures and engages the one or more semiconductor channel layers. The gate spacer is in contact with a sidewall of the gate metal layer. From a cross-section view, a neck portion of the gate metal layer adjacent to and along the one or more semiconductor channel layers, and one side of the neck portion is retracted by a distance relative to the gate spacer, and the distance is greater than 0 and less than or equal to 2 nanometers.
    Type: Application
    Filed: August 28, 2022
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Ting Pan, Kuo-Cheng Chiang, Chih-Hao Wang
  • Patent number: 11916072
    Abstract: A semiconductor device according to the present disclosure includes a first gate structure and a second gate structure aligned along a direction, a first metal layer disposed over the first gate structure, a second metal layer disposed over the second gate structure, and a gate isolation structure extending between the first gate structure and the second gate structure as well as between the first metal layer and the second metal layer.
    Type: Grant
    Filed: July 22, 2022
    Date of Patent: February 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jia-Chuan You, Chia-Hao Chang, Kuo-Cheng Chiang, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11916125
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a dielectric layer formed over a conductive feature; a semiconductor stack formed over the dielectric layer, wherein the semiconductor stack including semiconductor layers stacked up and separated from each other; a first metal gate structure and a second metal gate structure formed over a channel region of the semiconductor stack, wherein the first metal gate structure and the second metal gate structure wrap each of the semiconductor layers of the semiconductor stack; and a first epitaxial feature disposed between the first metal gate structure and the second metal gate structure over a first source/drain region of the semiconductor stack, wherein the first epitaxial feature extends through the dielectric layer and contacts the conductive feature.
    Type: Grant
    Filed: July 22, 2022
    Date of Patent: February 27, 2024
    Inventors: Chih-Chao Chou, Kuo-Cheng Chiang, Shi Ning Ju, Wen-Ting Lan, Chih-Hao Wang
  • Publication number: 20230378044
    Abstract: A flip-chip bonding structure includes a substrate and a chip. A lead of the substrate includes a body, a hollow opening, a bonding island and at least one connecting bridge. The hollow opening is in the body and surrounded by the body. The bonding island is located in the hollow opening such that there is a hollow space in the hollow opening and located between the body and the bonding island. The connecting bridge is located in the hollow space to connect the body and the bonding island. A bump of the chip is bonded to the bonding island by a solder. The solder is restricted on the bonding island and separated from the body by the hollow space so as to avoid the solder from overflowing to the body and avoid the chip from shifting.
    Type: Application
    Filed: February 14, 2023
    Publication date: November 23, 2023
    Inventors: Chin-Tang Hsieh, Lung-Hua Ho, Chih-Ming Kuo, Chun-Ting Kuo, Yu-Hui Hu, Chih-Hao Chiang, Chen-Yu Wang, Kung-An Lin, Pai-Sheng Cheng
  • Patent number: 11193060
    Abstract: Provided is a method for synthesizing a perovskite quantum dot film, including: preparing a cellulose nanocrystal (CNC) solution, wherein the CNC solution includes a plurality of CNCs with sulfate groups; preparing a precursor solution; mixing the CNC solution and the precursor solution to form a mixed solution; and filtering and drying the mixed solution to form a perovskite quantum dot film.
    Type: Grant
    Filed: January 20, 2020
    Date of Patent: December 7, 2021
    Assignees: National Taiwan University of Science and Technology, NATIONAL TAIWAN NORMAL UNIVERSITY, National Taiwan University
    Inventors: Chih-Hao Chiang, Ting-You Li, Meng-Lin Tsai, Ya-Ju Lee, Hsiang-Chieh Lee
  • Publication number: 20210171829
    Abstract: Provided is a method for synthesizing a perovskite quantum dot film, including: preparing a cellulose nanocrystal (CNC) solution, wherein the CNC solution includes a plurality of CNCs with sulfate groups; preparing a precursor solution; mixing the CNC solution and the precursor solution to form a mixed solution; and filtering and drying the mixed solution to form a perovskite quantum dot film.
    Type: Application
    Filed: January 20, 2020
    Publication date: June 10, 2021
    Applicants: National Taiwan University of Science and Technology, NATIONAL TAIWAN NORMAL UNIVERSITY, National Taiwan University
    Inventors: Chih-Hao Chiang, Ting-You Li, Meng-Lin Tsai, Ya-Ju Lee, Hsiang-Chieh Lee
  • Patent number: 8766654
    Abstract: A package structure with conformal shielding includes a substrate providing electrically connected inner grounding structures, a chip module mounted on the substrate, a molding compound covering the chip module and one surface of the substrate, and a conductive shielding layer covering the molding compound and the lateral sides of the substrate, and electrically connected with a part of the inner grounding structures. The substrate further provides one or multiple independent conductive structures electrically connected with the conductive shielding layer and exposed to the outside. By measuring the resistance value between one independent conductive structure and the conductive shielding layer or another independent conductive structure or one ground contact and then comparing the measured resistance value with a predetermined reference value, the EMI shielding performance of the package structure is determined.
    Type: Grant
    Filed: March 27, 2012
    Date of Patent: July 1, 2014
    Assignees: Universal Scientific Industrial Co., Ltd., Universal Global Scientific Industrial Co., Ltd.
    Inventors: Jaw-Ming Ding, Chien-Yeh Liu, Chih-Hao Chiang
  • Publication number: 20130257462
    Abstract: A package structure with conformal shielding includes a substrate providing electrically connected inner grounding structures, a chip module mounted on the substrate, a molding compound covering the chip module and one surface of the substrate, and a conductive shielding layer covering the molding compound and the lateral sides of the substrate, and electrically connected with a part of the inner grounding structures. The substrate further provides one or multiple independent conductive structures electrically connected with the conductive shielding layer and exposed to the outside. By measuring the resistance value between one independent conductive structure and the conductive shielding layer or another independent conductive structure or one ground contact and then comparing the measured resistance value with a predetermined reference value, the EMI shielding performance of the package structure is determined.
    Type: Application
    Filed: March 27, 2012
    Publication date: October 3, 2013
    Applicants: UNIVERSAL GLOBAL SCIENTIFIC INDUSTRIAL CO., LTD., UNIVERSAL SCIENTIFIC INDUSTRIAL CO., LTD.
    Inventors: Jaw-Ming DING, Chien-Yeh Liu, Chih-Hao Chiang
  • Patent number: 7187508
    Abstract: A lens device includes: a housing formed with a module-mounting hole that has a hole axis, and provided with a mounting surface that is disposed radially and outwardly of the module-mounting hole; a lens module having a lens axis; and an alignment correction unit for mounting the lens module on the housing at the module-mounting hole. The alignment correction unit includes a module barrel coupled to the lens module, an elastically deformable component clamped by the module barrel toward the mounting surface of the housing, and a set of screw fasteners for fastening the module barrel onto the mounting surface at angularly spaced apart locations relative to the hole axis. Depths of threaded engagement of the screw fasteners with the mounting surface are independently adjustable to permit adjustment of the lens axis of the lens module relative to the hole axis of the module-mounting hole.
    Type: Grant
    Filed: November 10, 2005
    Date of Patent: March 6, 2007
    Assignee: Asia Optical Co., Inc.
    Inventor: Chih-Hao Chiang
  • Publication number: 20060181786
    Abstract: A lens device includes: a housing formed with a module-mounting hole that has a hole axis, and provided with a mounting surface that is disposed radially and outwardly of the module-mounting hole; a lens module having a lens axis; and an alignment correction unit for mounting the lens module on the housing at the module-mounting hole. The alignment correction unit includes a module barrel coupled to the lens module, an elastically deformable component clamped by the module barrel toward the mounting surface of the housing, and a set of screw fasteners for fastening the module barrel onto the mounting surface at angularly spaced apart locations relative to the hole axis. Depths of threaded engagement of the screw fasteners with the mounting surface are independently adjustable to permit adjustment of the lens axis of the lens module relative to the hole axis of the module-mounting hole.
    Type: Application
    Filed: November 10, 2005
    Publication date: August 17, 2006
    Inventor: Chih-Hao Chiang