Abstract: A shock-absorbing and crash-preventing box includes a bottom surface; a side surface, said side surface has a multiple card hook supporters, said bottom surface and said side surface together can make a closed box-like body; and a flexible elastic net, comprising: a plurality of card-holding units, separately couple with the positioning portions; a positioning portion, provides an object a place to put; and an elastic section, said elastic section coupled between said plurality of card-holding and said object positioning section. As a result, when said object is placed on said flexible elastic net, said plurality of flexible openings will be pulled and stretched so that said object can be coated in said cover-up box-shaped body to present a dangling and a hanging stage.

Abstract: The single-step debug card using the PCI interface according to the present invention utilizes a bus master to send out an REQ# signal to request issuing a control during the PCI bus cycle to be inspected. The address, data, command, and byte enable (BE#) of the bus cycle are locked and displayed through LEDs for single-step debugging. Through a switch circuit, a TRDY# ready signal is sent out. A device selection signal (DEVSEL#) is raised to HIGH at the same time the TRDY# ready signal finishes so as to notify the bus master on the single-step interruption debug card to end the cycle for single-step debugging.

Abstract: This specification discloses a single step debug card using the PCI bus, which keeps the FRAME# of the PCI bus at a low voltage; latches and displays through an LED the address and command of the PCI bus cycle; keeps the control signal of read only memory and the IRDY# ready signal and TRDY# ready signal on the PCI bus at a low voltage, latches and displays through an LED the data and byte enable of the PCI bus cycle; outputs a device selection signal from a target device when the target device is detected; intercepts the PCI bus cycle when the device selection signal is kept at a low voltage and both the IRDY# ready signal and the TRDY# ready signal are kept at a low voltage; enables the PCI host to provide a retry function when the target device cannot respond a TRDY# ready signal before the PCI bus cycle ends so as to achieve the function of single step interruption debugging.

Abstract: The single-step debug card using the PCI interface according to the present invention utilizes a bus master to send out an REQ# signal to request issuing a control during the PCI bus cycle to be inspected. The address, data, command, and byte enable (BE#) of the bus cycle are locked and displayed through LEDs for single-step debugging. Through a switch circuit, a TRDY# ready signal is sent out. A device selection signal (DEVSEL#) is raised to HIGH at the same time the TRDY# ready signal finishes so as to notify the bus master on the single-step interruption debug card to end the cycle for single-step debugging.

Abstract: This specification discloses a single step debug card using the PCI bus, which keeps the FRAME# of the PCI bus at a low voltage; latches and displays through an LED the address and command of the PCI bus cycle; keeps the control signal of read only memory and the IRDY# ready signal and TRDY# ready signal on the PCI bus at a low voltage, latches and displays through an LED the data and byte enable of the PCI bus cycle; outputs a device selection signal from a target device when the target device is detected; intercepts the PCI bus cycle when the device selection signal is kept at a low voltage and both the IRDY# ready signal and the TRDY# ready signal are kept at a low voltage; enables the PCI host to provide a retry function when the target device cannot respond a TRDY# ready signal before the PCI bus cycle ends so as to achieve the function of single step interruption debugging.