Abstract: According to one example, a semiconductor device includes a substrate and a fin stack that includes a plurality of nanostructures, a gate device surrounding each of the nanostructures, and inner spacers along the gate device and between the nanostructures. A width of the inner spacers differs between different layers of the fin stack.

Abstract: A method for forming a semiconductor device is provided. The method includes forming a plurality of first channel nanostructures and a plurality of second channel nanostructures in an n-type device region and a p-type device region of a substrate, respectively, and sequentially depositing a gate dielectric layer, an n-type work function metal layer, and a cap layer surrounding each of the first and second channel nanostructures. The cap layer merges in first spaces between adjacent first channel nanostructures and merges in second spaces between adjacent second channel nanostructures. The method further includes selectively removing the cap layer and the n-type work function metal layer in the p-type device region, and depositing a p-type work function metal layer over the cap layer in the n-type device region and the gate dielectric layer in the p-type device region. The p-type work function metal layer merges in the second spaces.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first metal layer over a substrate, forming a dielectric layer over the first metal layer. The method includes forming a trench in the dielectric layer, and performing a surface treatment process on a sidewall surface of the trench to form a hydrophobic layer. The hydrophobic layer is formed on a sidewall surface of the dielectric layer. The method further includes depositing a metal material in the trench and over the hydrophobic layer to form a via structure.

Abstract: An image sensing device and a control device of an illumination device thereof are provided. The control device includes a control circuit, an operation circuit, and multiple driving signal generators. The control circuit generates multiple control signals. The operation circuit performs a logical operation on the control signals and an image capturing signal to generate multiple operation results. The driving signal generator respectively provides multiple driving signals to the illumination device according to the operation results, and the driving signals respectively have multiple different output powers.

Abstract: In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes a substrate. A gate electrode is over the substrate and a spacer structure laterally surrounds the gate electrode. A conductive via is disposed on the gate electrode. A liner is arranged along one or more sidewalls of the spacer structure. The conductive via has a bottommost surface that has a larger width than a part of the conductive via that is laterally adjacent to one or more interior sidewalls of the liner.

Abstract: In some embodiments, an image sensor is provided. The image sensor includes a photodetector disposed in a semiconductor substrate. A wave guide filter having a substantially planar upper surface is disposed over the photodetector. The wave guide filter includes a light filter disposed in a light filter grid structure. The light filter includes a first material that is translucent and has a first refractive index. The light filter grid structure includes a second material that is translucent and has a second refractive index less than the first refractive index.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first insulating layer over a substrate. A first metal feature is formed in the first insulating layer and a second insulating layer is formed over the first insulating layer. A first metal via is formed through the second insulating layer to connect the first metal feature. A second metal feature is formed over the second insulating layer. The second metal feature has a convex top surface and a plane bottom surface, and the plane bottom is electrically connected to the first metal feature through the first metal via.

Abstract: The federated learning system includes a moderator and client devices. Each client device performs a method for verifying model update as follows: receiving a hash function and a general model; training a client model according to the general model and raw data; calculating a difference as an update parameter between the general model and the client model, sending the update parameter to the moderator; inputting the update parameter to the hash function to generate a hash value; sending the hash value to other client devices, and receiving other hash values; summing all the hash values to generate a trust value; receiving an aggregation parameter calculated according to the update parameters; inputting the aggregation parameter to the hash function to generate a to-be-verified value; and updating the client model according to the aggregation parameter when the to-be-verified value equals the trust value.

Abstract: A conductive mechanism includes two bases, an inner conductive spring and an outer conductive spring. The two bases are opposite to each other. Each of the bases includes a surface and a partition wall protruding relative to the surface. The inner conductive spring is disposed at inner sides of the two partition walls of the two bases. The outer conductive spring is disposed at outer sides of the two partition walls of the two bases. At least one of two ends of each of the inner conductive spring and the outer conductive spring rotatably abuts against the surface of one of the bases.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes a first photodetector disposed in a first pixel region of a semiconductor substrate and a second photodetector disposed in a second pixel region of the semiconductor substrate. The second photodetector is laterally separated from the first photodetector. A first diffuser is disposed along a back-side of the semiconductor substrate and over the first photodetector. A second diffuser is disposed along the back-side of the semiconductor substrate and over the second photodetector. A first midline of the first pixel region and a second midline of the second pixel region are both disposed laterally between the first diffuser and the second diffuser.

Abstract: A semiconductor structure includes one or more channel layers; a gate structure engaging the one or more channel layers; a first source/drain feature connected to a first side of the one or more channel layers and adjacent to the gate structure; a first dielectric cap disposed over the first source/drain feature, wherein a bottom surface of the first dielectric cap is below a top surface of the gate structure; a first via disposed under and electrically connected to the first source/drain feature; and a power rail disposed under and electrically connected to the first via.

Abstract: The present disclosure provides a connecting device and a lamp system. The connecting device is used to connect multiple lamps to form the lamp system. The connecting device includes a connecting element, a cover, and a shell. The cover is mounted on the connecting element and includes at least two first assembling members. The shell is detachably mounted on the cover. The shell includes a side wall, an opening, multiple gateways, and at least two second assembling members. The side wall surrounds a space. The opening and the gateways all are formed on a top of the side wall and communicate with the space. A portion of each of the lamps is received in one of the gateways. The second assembling members are disposed on the side wall and face each other in a radial line of the shell, and respectively engage with the first assembling members.

Abstract: Semiconductor devices including air spacers formed in a backside interconnect structure and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure; and a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including a first dielectric layer on the backside of the first transistor structure; a first via extending through the first dielectric layer, the first via being electrically coupled to a first source/drain region of the first transistor structure; a first conductive line electrically coupled to the first via; and an air spacer adjacent the first conductive line, the first conductive line defining a first side boundary of the air spacer.

Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a gate structure sandwiched between and in contact with a first spacer feature and a second spacer feature, a top surface of the first spacer feature and a top surface of the second spacer feature extending above a top surface of the gate structure, a gate self-aligned contact (SAC) dielectric feature over the first spacer feature and the second spacer feature, a contact etch stop layer (CESL) over the gate SAC dielectric feature, a dielectric layer over the CESL, a gate contact feature extending through the dielectric layer, the CESL, the gate SAC dielectric feature, and between the first spacer feature and the second spacer feature to be in contact with the gate structure, and a liner disposed between the first spacer feature and the gate contact feature.

Abstract: A projection system includes a projector configured to project image light and furniture on which the projector is mounted. The furniture includes a furniture main body, a setting section provided in the furniture main body and houses the projector, and an opening and closing member provided in an opening through which the image light passes, the opening and closing member switching a closed state in which the opening is closed and an open state in which the opening is opened. By aligning the opening and closing member with a position corresponding to a projection surface in the open state, a position of the projector is determined in a predetermined projection position with respect to the projection surface. The projector projects the image light onto the projection surface from the predetermined projection position to thereby form a rectangular projection image on the projection surface.

Abstract: A projection system includes a projector configured to project image light and furniture on which the projector is mounted. The furniture includes a furniture main body, a setting section provided in the furniture main body and houses the projector, and an opening and closing member provided in an opening through which the image light passes, the opening and closing member switching a closed state in which the opening is closed and an open state in which the opening is opened. By aligning the opening and closing member with a position corresponding to a projection surface in the open state, a position of the projector is determined in a predetermined projection position with respect to the projection surface. The projector projects the image light onto the projection surface from the predetermined projection position to thereby form a rectangular projection image on the projection surface.

Abstract: An integrated circuit for driving a display panel and an anti-interference method are provided. The integrated circuit can include a source driving circuit and an anti-interference circuit. The source driving circuit includes a receiving circuit configured to receive an input signal including image data and process the input signal based on at least one operation parameter to generate output data. The anti-interference circuit is coupled to the receiving circuit. The anti-interference circuit can determine whether an interference event occurs to the input signal based on the input signal or the output data to obtain a determination result and determines whether to adjust the at least one operation parameter of the receiving circuit according to the determination result.

Abstract: A clock and data recovery device and a jitter tolerance enhancement method thereof are provided. The clock and data recovery device includes a clock and data recovery circuit and a jitter tolerance enhancement circuit. A data input terminal of the clock and data recovery circuit is suitable for receiving a data signal. The clock and data recovery circuit recovers the data signal to a clock. The jitter tolerance enhancement circuit is coupled to the data input terminal of the clock and data recovery circuit to receive the data signal. The jitter tolerance enhancement circuit detects a correlation between the data signal and the clock and correspondingly adjusts a loop gain of the clock and data recovery circuit according to the correlation.

Abstract: A line structure for fan-out circuit having a dense-line area and a fan-out area is provided. The line structure includes a plurality of dense lines arranged in the dense-line area parallel to a first direction, a plurality of pads disposed in the fan-out area, and a plurality of connecting lines arranged in the fan-out area parallel to a second direction. The connecting lines respectively connect one of the dense lines with one of the pads, wherein at least one of the connecting lines is a wavy line.

Abstract: An integrated circuit for driving a display panel and an anti-interference method are provided. The integrated circuit includes a source driving circuit and an anti-interference circuit. The source driving circuit includes a receiving circuit configured to receive an input signal including image data and process the input signal based on at least one operation parameter to generate output data. The anti-interference circuit is coupled to the receiving circuit. The anti-interference circuit is configured to adjust the at least one operation parameter of the receiving circuit from at least one normal parameter to at least one anti-interference parameter when an interference event occurs to the input signal. The anti-interference circuit is configured to maintain the at least one operation parameter of the receiving circuit at the at least one normal parameter when the interference event does not occur.