Abstract: A controlling method for semiconductor process auxiliary apparatus, a control assembly and a manufacturing system are provided. The controlling method includes the following steps. At least one manufacturing parameter of a semiconductor manufacturing processing apparatus are obtained. An energy adjusting signal is generated according to the manufacturing parameter. An auxiliary apparatus controlling signal is generated according to the energy adjusting signal. The semiconductor process auxiliary apparatus is controlled according to the semiconductor auxiliary apparatus controlling signal.

Abstract: A control system includes multiple device controllers and a device root. Each of the multiple device controllers corresponds to at least one processing unit, and is arranged to receive a hint from an application processor (AP), and generate a control signal for managing the at least one processing unit according to the hint. The device root is coupled to the multiple device controllers and includes a manager, wherein the manager is arranged to manage multiple processing units corresponding to the multiple device controllers according to multiple control signals corresponding to the multiple device controllers.

Abstract: A system for model protection includes a processor. The processor is arranged to execute a guest virtual machine (VM), a primary VM, and a hypervisor. The guest VM includes a model, and is arranged to send at least one command to a command hub. The primary VM is arranged to refer to the at least one command sent from the command hub to manage and configure a protection setting for a protected model derived from the model. The hypervisor is arranged to receive a safety setting command sent by the primary VM, and manage and configure the safety protection component according to the safety setting command, to set a read-only mode of the protected model.

Abstract: A power management system includes at least one device, at least one memory management unit (MMU), a processor, and at least one device controller, wherein the at least one MMU corresponds to the at least one device, respectively. The processor is arranged to execute at least one access control power manager, an operating system (OS), and a hypervisor, wherein the OS is arranged to generate a trigger signal, and the hypervisor is arranged to generate a first hint according to the trigger signal. The at least one device controller is arranged to control the at least one access control power manager according to the first hint, to manage at least one power of the at least one MMU.

Abstract: Aspects of the disclosure provide a method and an apparatus for executing a program, e.g., a neural network (NN) inference. For example, the apparatus can include an executor and a dynamic loading agent. The executor can be coupled to a second memory, and be configured to execute a portion of the NN inference loaded on the second memory from a first memory that stores the NN inference, and to generate a signal based on a progress of the execution of the NN inference. The dynamic loading agent can be coupled to the executor, the first memory and the second memory, and be configured to load a next portion of the NN inference stored in the first memory to the second memory and to manage power supplied to the first memory based on the signal from the executor and an inference executing scheme stored in the second memory.

Abstract: A virtual machine (VM) operating system (OS) device assignment system includes a processor, wherein the processor is configured to execute a host VM, a hypervisor, a device assigner, and a guest VM. The host VM is arranged to generate a driving signal for driving a booting of the guest VM. The hypervisor is arranged to generate a first trigger signal according to the driving signal, for triggering assignment of at least one device. The device assigner is arranged to modify a descriptor to generate a modified descriptor for assigning the at least one device among a plurality of devices to the guest VM, and install the modified descriptor into a protected memory, wherein an OS of the guest VM is configured according to the modified descriptor.

Abstract: Aspects of the present disclosure provide an apparatus that can execute an artificial intelligence (AI) model with IO changing. For example, the apparatus can include a first secured processor, a secured application embedded in the first secured processor and associated with an AI model, a secured memory configured to store an AI executable binary associated with the AI model, a second secured processor configured to execute the AI executable binary, a sub-system configured to trigger IO changing and trigger the second secured processor to execute the AI executable binary, IO meta data stored in the secured memory, an IO verifier configured to verify IO changing by determining the IO meta data, and an IO pre-fire module configured to patch the IO changing to the AI executable binary running on the second secured processor when the IO verifier determines that the IO changing matches the IO meta data.

Abstract: In an automatic test system, a test computer of a kind of test equipment communicates with a loading-and-unloading computer of a kind of loading-and-unloading equipment. The loading-and-unloading equipment automatically loads a plurality of target devices on a plurality of test carriers according to the state of the test equipment, and the test equipment automatically tests the target devices loaded on the test carriers according to the state of the loading-and-unloading equipment. In addition, after the test is completed, the loading-and-unloading equipment automatically unloads the tested target devices from the test carriers, and automatically sorts the tested target devices according to the test results generated by the test equipment.

Abstract: A virtual machine (VM) operating system (OS) configuration system includes a processor, wherein the processor is arranged to execute a host VM, a hypervisor, a descriptor provider, and a guest VM. The host VM is arranged to generate a driving signal for driving a booting of the guest VM. The hypervisor is arranged to generate a first trigger signal according to the driving signal, for triggering installation of a descriptor. The descriptor provider includes the descriptor, and is arranged to install the descriptor into a protected memory according to the first trigger signal, wherein an OS of the guest VM is configured according to the descriptor.

Abstract: Aspects of the present disclosure provide a video playback system. For example, the video playback system can include a video controller configured to receive one or more video frames and partition each of the video frames into a plurality of video tiles, a video decoder configured to decode one of the video tiles partitioned from each of the video frames, an artificial intelligence (AI) accelerator configured to execute an executable AI model on the decoded video tile, a display configured to display the processed video tile, and a pipeline manager installed in the video controller. The pipeline manager can be configured to control the video decoder to decode the video tile, control the AI accelerator to execute the executable AI model on the decoded video tile, and control the display to display the processed video tile.

Abstract: A system includes a memory addressable by addresses within a physical address (PA) space, and one or more processors that perform operations of virtual machines (VMs). The VMs are allocated with extended PA regions outside the PA space. The system further includes a memory interface controller coupled to the memory and the one or more processors. The memory interface controller receives a request for accessing an address in the extended PA regions from a requesting VM, and uses a remap circuit to map the address in the extended PA regions to a remapped address in the PA space. A memory protection unit (MPU) in the memory interface controller grants or denies the request based on stored information indicating whether the remapped address is accessible to the requesting VM.

Abstract: A computing system includes a memory, an MPU, and a processor. The MPU is arranged to: receive permission information of the memory; and perform a protection operation through a dynamic firewall. The processor is arranged to execute a root manager and a hypervisor. The root manager is arranged to provide the permission information to the MPU. The hypervisor is arranged to: receive the permission information from the MPU; set the dynamic firewall according to the permission information; and provide the dynamic firewall to the MPU.

Abstract: A virtual machine (VM) operating system (OS) configuration system includes a processor, wherein the processor is arranged to execute a host VM, a hypervisor, a root module, and a guest VM. The host VM is arranged to generate a driving signal for driving a booting of a guest VM. The hypervisor is arranged to generate a first trigger signal according to the driving signal, for triggering verification of a descriptor. The root module is arranged to verify the descriptor according to the first trigger signal to generate a verified descriptor, and store the verified descriptor in a protected memory, wherein an OS of the guest VM is configured according to the verified descriptor.

Abstract: A system on chip includes a secure processing unit (SPU), an artificial intelligence/machine learning accelerator (AI/ML accelerator), a memory inline cypher engine, and a central processing unit (CPU). The SPU is used to store biometrics of users. The AI/ML accelerator is used to process images, and analyze the biometrics of users. The AI/ML accelerator includes a micro control unit (MCU) for intelligently linking access identifications (IDs) to version numbers (VNs). The inline cypher engine is coupled to the AI/ML accelerator and the SPU for receiving a register file from the MCU, encrypting data received from the AI/ML accelerator, and comparing the biometrics of the users received from the SPU with the data. The CPU is coupled to the SPU and the AI/ML accelerator for controlling the SPU and the AI/ML accelerator.

Abstract: A system on chip includes a secure processing unit (SPU), an artificial intelligence/machine learning accelerator (AI/ML accelerator), a memory inline cypher engine, and a central processing unit (CPU). The SPU is used to store biometrics of users. The AI/ML accelerator is used to process images, and analyze the biometrics of users. The AI/ML accelerator includes a micro control unit (MCU) for intelligently linking access identifications (IDs) to version numbers (VNs). The inline cypher engine is coupled to the AI/ML accelerator and the SPU for receiving a register file from the MCU, encrypting data received from the AI/ML accelerator, and comparing the biometrics of the users received from the SPU with the data. The CPU is coupled to the SPU and the AI/ML accelerator for controlling the SPU and the AI/ML accelerator.

Abstract: A control system includes multiple device controllers and a device root. Each of the multiple device controllers corresponds to at least one processing unit, and is arranged to receive a hint from an application processor (AP), and generate a control signal for managing the at least one processing unit according to the hint. The device root is coupled to the multiple device controllers and includes a manager, wherein the manager is arranged to manage multiple processing units corresponding to the multiple device controllers according to multiple control signals corresponding to the multiple device controllers.

Abstract: A device includes a substrate, a chalcogenide channel layer, a chalcogenide barrier layer, source/drain contacts, and a gate electrode. The chalcogenide channel layer is over the substrate. The chalcogenide barrier layer is over the chalcogenide channel layer. A dopant concentration of the chalcogenide barrier layer is greater than a dopant concentration of the chalcogenide channel layer. The source/drain contacts are over the chalcogenide channel layer. The gate electrode is over the substrate.

Abstract: In an automatic test system, a test computer of a kind of test equipment communicates with a loading-and-unloading computer of a kind of loading-and-unloading equipment. The loading-and-unloading equipment automatically loads a plurality of target devices on a plurality of test carriers according to the state of the test equipment, and the test equipment automatically tests the target devices loaded on the test carriers according to the state of the loading-and-unloading equipment. In addition, after the test is completed, the loading-and-unloading equipment automatically unloads the tested target devices from the test carriers, and automatically sorts the tested target devices according to the test results generated by the test equipment.

Abstract: A device includes a substrate, a channel layer, a barrier layer, a gate electrode, and source/drain contacts. The channel layer is made of transition metal dichalcogenide. The barrier layer is over the channel layer. The gate electrode is over the barrier layer. The source/drain contacts are on opposite sides of the gate electrode and over the barrier layer.

Abstract: Aspects of the present disclosure provide an apparatus, which can include a first secured processor and secured applications embedded in the first secured processor. Each of the secured applications can be associated with an artificial intelligence (AI) model. The apparatus can further include first secured memories each configured to store an AI executable binary associated with a corresponding one of the AI models, a second secured processor configured to execute the AI executable binaries stored in the first secured memories, a sub-system, and an AI session manager configured to receive from the sub-system an AI session that identifies one of the AI models, and prepare and store an AI executable binary associated with the AI model to one of the first secured memories that corresponds to the AI executable binary. The sub-system can trigger the second secured processor to execute the AI executable binary stored in the first secured memory.