Abstract: A system on chip includes a secure processing unit (SPU), an artificial intelligence/machine learning accelerator (AI/ML accelerator), a memory inline cypher engine, and a central processing unit (CPU). The SPU is used to store biometrics of users. The AI/ML accelerator is used to process images, and analyze the biometrics of users. The AI/ML accelerator includes a micro control unit (MCU) for intelligently linking access identifications (IDs) to version numbers (VNs). The inline cypher engine is coupled to the AI/ML accelerator and the SPU for receiving a register file from the MCU, encrypting data received from the AI/ML accelerator, and comparing the biometrics of the users received from the SPU with the data. The CPU is coupled to the SPU and the AI/ML accelerator for controlling the SPU and the AI/ML accelerator.

Abstract: A handwriting data processing method is applied to a pen display having wireless communication function and a data processing device. The handwriting data processing method includes the steps of: the data processing device obtaining a handwriting data from the pen display in a wireless communication manner; the data processing device generating a compressed screen image and transmitting the data of the compressed screen image and the handwriting data, which is not compressed, to the pen display in the wireless communication manner; the pen display uncompressing the data of the compressed screen image and overlapping the uncompressed screen image and the handwriting data to form a complete screen image and displaying the complete screen image. By the handwriting processing method, the machine time of the processor of the pen display is effectively lowered, significantly reducing the delay phenomenon of the displayed handwriting.

Abstract: A control system includes multiple device controllers and a device root. Each of the multiple device controllers corresponds to at least one processing unit, and is arranged to receive a hint from an application processor (AP), and generate a control signal for managing the at least one processing unit according to the hint. The device root is coupled to the multiple device controllers and includes a manager, wherein the manager is arranged to manage multiple processing units corresponding to the multiple device controllers according to multiple control signals corresponding to the multiple device controllers.

Abstract: A device includes a substrate, a chalcogenide channel layer, a chalcogenide barrier layer, source/drain contacts, and a gate electrode. The chalcogenide channel layer is over the substrate. The chalcogenide barrier layer is over the chalcogenide channel layer. A dopant concentration of the chalcogenide barrier layer is greater than a dopant concentration of the chalcogenide channel layer. The source/drain contacts are over the chalcogenide channel layer. The gate electrode is over the substrate.

Abstract: In an automatic test system, a test computer of a kind of test equipment communicates with a loading-and-unloading computer of a kind of loading-and-unloading equipment. The loading-and-unloading equipment automatically loads a plurality of target devices on a plurality of test carriers according to the state of the test equipment, and the test equipment automatically tests the target devices loaded on the test carriers according to the state of the loading-and-unloading equipment. In addition, after the test is completed, the loading-and-unloading equipment automatically unloads the tested target devices from the test carriers, and automatically sorts the tested target devices according to the test results generated by the test equipment.

Abstract: A device includes a substrate, a channel layer, a barrier layer, a gate electrode, and source/drain contacts. The channel layer is made of transition metal dichalcogenide. The barrier layer is over the channel layer. The gate electrode is over the barrier layer. The source/drain contacts are on opposite sides of the gate electrode and over the barrier layer.

Abstract: A device can include a remote protocol communication (RPC) slot configured to receive a message package generated from an entity during an RPC process, a processing unit configured to process the message package and return a result via the RPC slot to the entity, a blocker configured to be enabled to block or disabled to allow communication between the RPC slot and the processing unit, a key slot corresponding to the RPC slot and configured to receive a key from the entity, a key pool configured to store key slot and key pairs, and a verifier configured to disable the blocker when the key matches a key contained in one of the key slot and key pairs that contains the key slot and enable the blocker when the key does not match the key contained in any one of the key slot and key pairs that contains the key slot.

Abstract: Aspects of the present disclosure provide an apparatus, which can include a first secured processor and secured applications embedded in the first secured processor. Each of the secured applications can be associated with an artificial intelligence (AI) model. The apparatus can further include first secured memories each configured to store an AI executable binary associated with a corresponding one of the AI models, a second secured processor configured to execute the AI executable binaries stored in the first secured memories, a sub-system, and an AI session manager configured to receive from the sub-system an AI session that identifies one of the AI models, and prepare and store an AI executable binary associated with the AI model to one of the first secured memories that corresponds to the AI executable binary. The sub-system can trigger the second secured processor to execute the AI executable binary stored in the first secured memory.

Abstract: Aspects of the disclosure provide an apparatus for executing a program that involves a plurality of operators. For example, the apparatus can include an executor and an analyzer. The executor can be configured to execute the program with at least a first one of the operators loaded on a second memory from a first memory that stores the operators and to generate a signal based on a progress of the execution of the program with the first operator. The analyzer can be coupled to the executor, the first memory and the second memory, and configured to load at least a second one of the operators of the program next to the first operator stored in the first memory to the second memory before the executor finishes execution of the program with the first operator based on the signal from the executor and an executing scheme stored in the second memory.

Abstract: The present invention provides a microcontroller, wherein the microcontroller includes a processor, a first memory and a cache controller. The first memory includes at least a working space. The cache controller is coupled to the first memory, and is arranged for managing the working space of the first memory, and dynamically loading at least one object from a second memory to the working space of the first memory in an object-oriented manner.

Abstract: A system for application (APP) protection includes a processor. The processor is arranged to execute a guest virtual machine (VM), at least one primary VM, a hypervisor, and a host VM, wherein at least one APP protection with at least one identification (ID) of the at least one APP running on the guest VM is downloaded to the guest VM. The hypervisor includes an install service module and a launcher module. The host VM is arranged to: receive at least one install command from the guest VM, and generate an install service command to the install service module; verify the at least one APP protection by the at least one ID and generate at least one verification result; obtain the at least one ID from the at least one primary VM according to the at least one verification result; and generate a launch command to the launcher module.

Abstract: A system for kernel protection includes a processor and a transmission interface. The processor is arranged to execute at least one guest virtual machine (VM), at least one primary VM, and a hypervisor. The at least one guest VM is arranged to send at least one command to a command hub. The at least one primary VM is arranged to manage and configure a safety setting according to the at least one command from the command hub and at least one policy, and manage and configure a safety protection component according to the safety setting. The hypervisor is arranged to manage and configure the safety protection component according to a ground rule and at least one safety setting command from the at least one primary VM. The transmission interface is arranged to bind the at least one primary VM to the hypervisor.

Abstract: A system for model protection includes a processor. The processor is arranged to execute a guest virtual machine (VM), a primary VM, and a hypervisor. The guest VM includes a model, and is arranged to send at least one command to a command hub. The primary VM is arranged to refer to the at least one command sent from the command hub to manage and configure a protection setting for a protected model derived from the model. The hypervisor is arranged to receive a safety setting command sent by the primary VM, and manage and configure the safety protection component according to the safety setting command, to set a read-only mode of the protected model.

Abstract: A computing system includes a processor, and the processor is arranged to execute: a guest virtual machine (VM), a hypervisor, and a primary VM, wherein an operating system (OS) runs on the guest VM, and an application (APP) runs on the OS. The kernel of the OS includes a protection service module and a memory management unit (MMU) manager. The protection service module is arranged to receive at least one virtual address and a first size information sent by a client of the APP. The primary VM includes a protection manager, and the protection manager is arranged to obtain a physical address array and a second size information according to the at least one virtual address and the first size information sent by the protection service through the hypervisor.

Abstract: A system controls access to a physical address (PA) space. The system includes multiple system resources addressable within the PA space, and multiple processing circuits executing multiple virtual machines (VMs). A given region of the PA space is dedicated to addressing the VMs. The system also includes multiple memory management units (MMUs) coupled to corresponding processing circuits. A given MMU is operative to translate a virtual address indicated in an access request from a processing circuit into a requested PA that is accessible by the processing circuit according to a configurable setting of the given MMU. The system further includes multiple memory protection units (MPUs). A given MPU, which is coupled to a target system resource allocated with the requested PA, is operative to grant or deny the request based on information indicating whether the requested PA is accessible to a requesting VM executed on the processing circuit.

Abstract: A device includes a substrate, a channel layer, a barrier layer, a gate electrode, and source/drain contacts. The channel layer is made of transition metal dichalcogenide. The barrier layer is over the channel layer. The gate electrode is over the barrier layer. The source/drain contacts are on opposite sides of the gate electrode and over the barrier layer.

Abstract: Aspects of the disclosure provide an apparatus for executing a program that involves a plurality of operators. For example, the apparatus can include an executor and an analyzer. The executor can be configured to execute the program with at least a first one of the operators loaded on a second memory from a first memory that stores the operators and to generate a signal based on a progress of the execution of the program with the first operator. The analyzer can be coupled to the executor, the first memory and the second memory, and configured to load at least a second one of the operators of the program next to the first operator stored in the first memory to the second memory before the executor finishes execution of the program with the first operator based on the signal from the executor and an executing scheme stored in the second memory.

Abstract: A semiconductor device includes a substrate, a channel stack, source/drain contacts, and a gate electrode. The channel stack is over the substrate and includes a 2D channel layer and a barrier layer. An energy band gap of the barrier layer is greater than an energy band gap of the 2D channel layer. The source/drain contacts are in contact with the channel stack. The gate electrode is above the substrate.

Abstract: A system includes a memory addressable by addresses within a physical address (PA) space, and one or more processors that perform operations of virtual machines (VMs). The VMs are allocated with extended PA regions outside the PA space. The system further includes a memory interface controller coupled to the memory and the one or more processors. The memory interface controller receives a request for accessing an address in the extended PA regions from a requesting VM, and uses a remap circuit to map the address in the extended PA regions to a remapped address in the PA space. A memory protection unit (MPU) in the memory interface controller grants or denies the request based on stored information indicating whether the remapped address is accessible to the requesting VM.

Abstract: Aspects of the disclosure provide a method and an apparatus for executing a program, e.g., a neural network (NN) inference. For example, the apparatus can include an executor and a dynamic loading agent. The executor can be coupled to a second memory, and be configured to execute a portion of the NN inference loaded on the second memory from a first memory that stores the NN inference, and to generate a signal based on a progress of the execution of the NN inference. The dynamic loading agent can be coupled to the executor, the first memory and the second memory, and be configured to load a next portion of the NN inference stored in the first memory to the second memory and to manage power supplied to the first memory based on the signal from the executor and an inference executing scheme stored in the second memory.