Abstract: An outer border, and a seal ring substantially co-extensive with and spaced from the outer border is disclosed. A plurality of fault detection chains extend from adjacent the outer border to within the seal ring. At least a first one of the plurality of fault detection chains includes a contact pad, a first metal feature coupled to the contact pad by a first via in a passivation layer, a second metal feature coupled to the first metal feature by a second via, and a substrate contact coupled to the second metal feature by a third via.

Abstract: Described are methods and structures for mitigating the effects of mechanical stresses placed on the layers of semiconductor devices, and specifically disclosed are methods and structures for mitigating the diminished chemical bonds between etch-stop layers and other semiconductor device layers. The disclosed methods and structures use different structures and/or processes for some of the etch-stop layers in a device.

Abstract: Described are methods and structures for mitigating the effects of mechanical stresses placed on the layers of semiconductor devices, and specifically disclosed are methods and structures for mitigating the diminished chemical bonds between etch-stop layers and other semiconductor device layers. The disclosed methods and structures use different structures and/or processes for some of the etch-stop layers in a device.

Abstract: A method to singulate a circuit die from an integrated circuit wafer is achieved. The method comprises providing an integrated circuit wafer containing a circuit die. The integrated circuit wafer is cut through by performing a single, continuous cut around the perimeter of the circuit die to thereby singulate the circuit die.

Abstract: A structure for reinforcing or anchoring a bond pad on a chip. The structure includes a bonding pad provided in a dielectric layer, at least one conductive layer provided beneath and in electrical contact with the bonding pad, and at least one parallel-interconnect anchor structure provided in contact with the bonding pad and the conductive layer. The anchor structure or structures prevent the bonding pad from exerting excessive force against the dielectric layer and cracking the dielectric layer when the chip is subjected to physical testing. The bonding pad may have truncated or curved corners, for example.

Abstract: A test pattern (100, 200, 300, 400, 600, 700) has a first metal structure (102) disposed on a substrate (352), one or more intermediate layers (358) disposed above the first metal structure (102) and a second metal structure (104) disposed above the one or more intermediate layers (352). A first via (106) passes through the intermediate layers (352) and connects the first metal structure (102) to the second metal structure (104). One or more third metal structures (108) are disposed above the one or more intermediate layers (352) and the first metal structure (102). One or more second vias (110) pass through the intermediate layers (352) and connect the first metal structure (102) to the third metal structures (108). The second vias (110) are located outside of a radius (R) from a center of the first via (106). The third metal structures (110) are separated from the second metal structure (104) by a dielectric material (366).

Abstract: A structure for reducing stress-induced voiding in an interconnect of an integrated circuit, the interconnect having a first portion and at least a second portion narrower than the first portion. The structure comprises at least one interior slot disposed in the first portion in proximity to the intersection of the first portion and the second portion. The present invention also includes methods of making the interconnect and the structure. A conductive interconnect structure comprises a first portion and at least a second portion narrower than the first portion; and a stress reducing structure comprising a transition portion formed at an intersection of the first portion and the second portion.

Abstract: A structure for reducing stress-induced voiding in an interconnect of an integrated circuit, the interconnect having a first portion and at least a second portion narrower than the first portion. The structure comprises at least one interior slot disposed in the first portion in proximity to the intersection of the first portion and the second portion. The present invention also includes methods of making the interconnect and the structure. A conductive interconnect structure comprises a first portion and at least a second portion narrower than the first portion; and a stress reducing structure comprising a transition portion formed at an intersection of the first portion and the second portion.

Abstract: A bond pad structure for an integrated circuit chip has a stress-buffering layer between a top interconnection level metal layer and a bond pad layer to prevent damages to the bond pad structure from wafer probing and packaging impacts. The stress-buffering layer is a conductive material having a property selected from the group consisting of Young's modulus, hardness, strength and toughness greater than the top interconnection level metal layer or the bond pad layer. For improving adhesion and bonding strength, the lower portion of the stress-buffering layer may be modified as various forms of a ring, a mesh or interlocking-grid structures embedded in a passivation layer, alternatively, the stress-buffering layer may has openings filled with the bond pad layer.

Abstract: A seal ring structure is disclosed for protecting a core circuit region of an integrated circuit chip. The seal ring structure includes a metallization layer, having a bridge sublevel and a plug sublevel. An upper-level bridge is formed on the bridge sublevel at a predetermined location between a peripheral edge of the integrated circuit chip and the core circuit region. A lower-level bridge is formed on the plug sublevel in substantial alignment with the upper-level bridge, wherein the lower-level bridge has a width substantially the same as that of the upper-level bridge.

Abstract: A wafer device is disclosed for improving reliability of circuits fabricated in an active area on a silicon substrate. A seal ring is fabricated around the active area, and a shallow trench isolation is also formed between the seal ring and a scribe line by etching into a portion of the silicon substrate, wherein the seal ring and the shallow trench isolation prevent die saw induced crack from propagating to the active area when the active area is cut along the scribe line.

Abstract: A method of forming an improved seal ring structure is described. A continuous metal seal ring is formed along a perimeter of a die wherein the metal seal ring is parallel to the edges of the die and sloped at the corner of the die so as not to have a sharp corner and wherein the metal seal ring has a first width at the corners and a second width along the edges wherein the first width is wider than the second width.

Abstract: A bond pad for a flip chip package. The bond pad is suitable for an integrated circuit chip. A plurality of slots are designed in the bond pad. Each of the slots extends along a direction which is perpendicular to a radial direction from the center of the bond pad. The bond pad is deposed at the corner of the integrated circuit chip.

Abstract: A method to singulate a circuit die from an integrated circuit wafer is achieved. The method comprises providing an integrated circuit wafer containing a circuit die. The integrated circuit wafer is cut through by performing a single, continuous cut around the perimeter of the circuit die to thereby singulate the circuit die.

Abstract: A test pattern (100, 200, 300, 400, 600, 700) has a first metal structure (102) disposed on a substrate (352), one or more intermediate layers (358) disposed above the first metal structure (102) and a second metal structure (104) disposed above the one or more intermediate layers (352). A first via (106) passes through the intermediate layers (352) and connects the first metal structure (102) to the second metal structure (104). One or more third metal structures (108) are disposed above the one or more intermediate layers (352) and the first metal structure (102). One or more second vias (110) pass through the intermediate layers (352) and connect the first metal structure (102) to the third metal structures (108). The second vias (110) are located outside of a radius (R) from a center of the first via (106). The third metal structures (110) are separated from the second metal structure (104) by a dielectric material (366).

Abstract: A chip orientation and attachment method is disclosed which eliminates or substantially reduces chip damage caused by thermal stress induced by application of a molding compound to the chip and substrate. The chip is attached to the substrate in such a manner that at least one of the following conditions exists: the chip diagonal and the substrate diagonal are in non-aligned relationship, and/or the chip edges are non-parallel with respect to the substrate edges, and/or the chip center is in non-overlapping relationship with respect to the substrate center. The invention includes chip package structures fabricated according to the chip orientation and attachment method.

Abstract: A structure for reinforcing or anchoring a bond pad on a chip. The structure includes a bonding pad provided in a dielectric layer, at least one conductive layer provided beneath and in electrical contact with the bonding pad, and at least one parallel-interconnect anchor structure provided in contact with the bonding pad and the conductive layer. The anchor structure or structures prevent the bonding pad from exerting excessive force against the dielectric layer and cracking the dielectric layer when the chip is subjected to physical testing. The bonding pad may have truncated or curved corners, for example.

Abstract: A bond pad for a flip chip package. The bond pad is suitable for an integrated circuit chip. A plurality of slots are designed in the bond pad. Each of the slots extends along a direction which is perpendicular to a radial direction from the center of the bond pad. The bond pad is deposed at the corner of the integrated circuit chip.

Abstract: A structure for a multi-level interconnect inter-level dielectric layer (ILD), a method of manufacturing thereof, and a semiconductor device including the ILD layer. The ILD layer includes a first low-dielectric constant material sub-layer, and a second low-dielectric constant material sub-layer disposed over the first low-dielectric constant material sub-layer. The second low-dielectric constant material sub-layer has at least one different material property than the first low-dielectric constant material sub-layer. A third low-dielectric constant material sub-layer is disposed over the second low-dielectric constant material sub-layer, the third low-dielectric constant material sub-layer having at least one different material property than the second low-dielectric constant material sub-layer.

Abstract: A test pattern (100, 200, 300, 400, 600, 700) has a first metal structure (102) disposed on a substrate (352), one or more intermediate layers (358) disposed above the first metal structure (102) and a second metal structure (104) disposed above the one or more intermediate layers (352). A first via (106) passes through the intermediate layers (352) and connects the first metal structure (102) to the second metal structure (104). One or more third metal structures (108) are disposed above the one or more intermediate layers (352) and the first metal structure (102). One or more second vias (110) pass through the intermediate layers (352) and connect the first metal structure (102) to the third metal structures (108). The second vias (110) are located outside of a radius (R) from a center of the first via (106). The third metal structures (110) are separated from the second metal structure (104) by a dielectric material (366).