Patents by Inventor Chih-Hsien Chang

Chih-Hsien Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11233081
    Abstract: In some embodiments, an image sensor is provided. The image sensor includes a photodetector disposed in a semiconductor substrate. A wave guide filter having a substantially planar upper surface is disposed over the photodetector. The wave guide filter includes a light filter disposed in a light filter grid structure. The light filter includes a first material that is translucent and has a first refractive index. The light filter grid structure includes a second material that is translucent and has a second refractive index less than the first refractive index.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: January 25, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng Yu Huang, Chun-Hao Chuang, Chien-Hsien Tseng, Kazuaki Hashimoto, Keng-Yu Chou, Wei-Chieh Chiang, Wen-Chien Yu, Ting-Cheng Chang, Wen-Hau Wu, Chih-Kung Chang
  • Patent number: 11228303
    Abstract: A controlling circuit for ring oscillator is provided. First and second transistors of a first conductive type are coupled in series and between a node and a first power source. Third and fourth transistors of a second conductive type are coupled in parallel and between the node and a second power source. The node is coupled to an input of a delay chain of the ring oscillator. The second and third transistors are coupled in series and gates of the second and third transistors are configured to receive an output signal of the delay chain. When the first transistor is turned off and the fourth transistor is turned on, the node is pulled to a first logic level from a second logic level in order to align a phase of a waveform of the ring oscillator.
    Type: Grant
    Filed: October 8, 2020
    Date of Patent: January 18, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Hsien Tsai, Ruey-Bin Sheen, Chih-Hsien Chang, Cheng-Hsiang Hsieh
  • Patent number: 11228304
    Abstract: A method and apparatus of generating precision phase skews is disclosed. In some embodiments, a phase skew generator includes: a charge pump having a first mode of operation and a second mode of operation, wherein the first mode of operation provides a first current path during a first time period, and the second mode of operation provides a second current path during a second time period following the first time period, a sample and hold circuit, coupled to a capacitor, and configured to sample a voltage level of the capacitor at predetermined times and provide an output voltage during a third time period following the second time period; and a voltage controlled delay line, coupled to the sample and hold circuit, and having M delay line stages each configured to output a signal having a phase skew offset with respect to preceding or succeeding signal.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: January 18, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mao-Hsuan Chou, Ya-Tin Chang, Ruey-Bin Sheen, Chih-Hsien Chang
  • Patent number: 11228279
    Abstract: Oscillators and methods for realignment of an oscillator are provided. An oscillator includes an inductor having first and second terminals and a capacitor electrically coupled in parallel to the inductor at the first and second terminals. A first transistor of a first conductivity type is electrically coupled to the first terminal and a voltage source. The first transistor includes a gate configured to receive a first realignment signal. When the first realignment signal is in a realignment state, the first transistor is turned on and a voltage of the first terminal is increased from a low level to a high level in order to align a phase of a waveform of the oscillator.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: January 18, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Tsung-Hsien Tsai, Ruey-Bin Sheen, Chih-Hsien Chang, Cheng-Hsiang Hsieh
  • Patent number: 11217524
    Abstract: The present disclosure provides an interconnect structure, including a first interlayer dielectric layer, a bottom metal line including a first metal in the first interlayer dielectric layer, a conductive via including a second metal over the bottom metal line, wherein the second metal is different from the first metal, and the first metal has a first type of primary crystalline structure, and the second metal has the first type of primary crystalline structure, a total area of a bottom surface of the conductive via is greater than a total cross sectional area of the conductive via, and a top metal line over the conductive via, wherein the top metal line comprises a third metal different from the second metal.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: January 4, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shuen-Shin Liang, Ken-Yu Chang, Hung-Yi Huang, Chien Chang, Chi-Hung Chuang, Kai-Yi Chu, Chun-I Tsai, Chun-Hsien Huang, Chih-Wei Chang, Hsu-Kai Chang, Chia-Hung Chu, Keng-Chu Lin, Sung-Li Wang
  • Patent number: 11211936
    Abstract: Digital delay lock circuits and methods for operating digital delay lock circuits are provided. A phase detector is configured to receive first and second clock signals and generate a digital signal indicating a relationship between a phase of the first clock signal and a phase of the second clock signal. A phase accumulator circuit is configured to receive the digital signal and generate a phase signal based on values of the digital signal over multiple clock cycles. A decoder is configured to receive the phase signal and generate a digital control word based on the phase signal. A delay element is configured to receive the digital control word. The delay element is further configured to change the relationship between the phase of the first clock signal and the phase of the second clock signal by modifying the phase of the second clock signal according to the digital control word.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: December 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Hsien Tsai, Ya-Tin Chang, Ruey-Bin Sheen, Chih-Hsien Chang, Cheng-Hsiang Hsieh
  • Publication number: 20210397073
    Abstract: A projector, including a body, a light source, a light valve, a projection lens, and a lens adjustment module, is provided. The light source and the light valve are disposed in the body, and the projection lens is movably disposed on the body. The lens adjustment module includes a driven structure connected to the projection lens, a guiding member and a rotating member connected to the guiding member. The guiding member is disposed on the body to be rotatable along an axis of rotation and has a closed ring guiding rail. The driven structure is slidably disposed at the closed ring guiding rail and is configured to move relative to the guiding member along a closed ring path defined by the closed ring guiding rail. A normal direction of a surface where the closed ring path is located is not parallel to the axis of rotation.
    Type: Application
    Filed: April 19, 2021
    Publication date: December 23, 2021
    Applicant: Coretronic Corporation
    Inventors: Chun-Hsien Wu, Chih-Hui Chang, Fu-Shun Kao
  • Patent number: 11201625
    Abstract: Phase-locked loops (PLLs) are provided. A PLL includes a voltage-controlled oscillator (VCO), a frequency divider and a track-and-hold charge pump. The VCO is configured to provide an output clock corresponding to a pumping current. The frequency divider is configured to provide a feedback signal according to the output clock. The track-and-hold charge pump is configured to provide the pumping current according to a reference clock and the feedback signal. The track-and-hold charge pump includes a track-and-hold circuit, a pumping switch and a pulse width modulator (PWM). The track-and-hold circuit is coupled to the frequency divider and configured to sample the feedback signal according to the reference clock. The PWM is configured to provide a PWM signal to control the pumping switch according to the reference clock, so as to provide the pumping current corresponding to the sampled feedback signal.
    Type: Grant
    Filed: October 13, 2020
    Date of Patent: December 14, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ting-Kuei Kuan, Cheng-Hsiang Hsieh, Chen-Ting Ko, Ruey-Bin Sheen, Chih-Hsien Chang
  • Publication number: 20210335991
    Abstract: An IC structure includes a resistor circuit and a transistor. The resistor circuit includes a first metal resistor strip over a semiconductor substrate, and a first metal line and a second metal line extending on a same level height above the first metal resistor strip. The first metal resistor strip is a dummy gate. Both the first metal line and the second metal line overlap and are electrically connected to the first metal resistor strip. The transistor includes a metal gate strip on a same level height as the first metal strip and extends in parallel with the first metal resistor strip.
    Type: Application
    Filed: February 4, 2021
    Publication date: October 28, 2021
    Inventors: Tien-Chien HUANG, Ruey-Bin SHEEN, Chih-Hsien CHANG
  • Publication number: 20210305975
    Abstract: A phase interpolating (PI) system includes: a phase-interpolating (PI) stage configured to receive first and second clock signals and a multi-bit weighting signal, and generate an interpolated clock signal, the PI stage being further configured to avoid a pull-up/pull-down (PUPD) short-circuit situation by using the multi-bit weighting signal and a logical inverse thereof (multi-bit weighting_bar signal); and an amplifying stage configured to receive and amplify the interpolated clock signal, the amplifying stage including a capacitive component; the capacitive component being tunable; and the capacitive component having a Miller effect configuration resulting in a reduced footprint of the amplifying stage.
    Type: Application
    Filed: September 14, 2020
    Publication date: September 30, 2021
    Inventors: Tsung-Che LU, Chin-Ming FU, Chih-Hsien CHANG
  • Publication number: 20210270879
    Abstract: Systems, methods, and circuits for determining a duty cycle of a periodic input signal are provided. A delay element is configured to delay the periodic input signal based on a digital control word. A digital circuit is configured to generate a first digital control word used to delay the periodic input signal a first amount of time corresponding to a period of the periodic input signal, generate a second digital control word used to delay the periodic input signal a second amount of time corresponding to a portion of the periodic input signal having a logic-level high value, and generate a third digital control word used to delay the periodic input signal a third amount of time corresponding to a portion of the periodic input signal having a logic-level low value. A controller is configured to determine the duty cycle based on the first, second, and third digital control words.
    Type: Application
    Filed: December 17, 2020
    Publication date: September 2, 2021
    Inventors: Tsung-Hsien Tsai, Ruey-Bin Sheen, Chih-Hsien Chang, Cheng-Hsiang Hsieh
  • Publication number: 20210258003
    Abstract: Systems, methods, and devices are provided for a circuit for generating a pulse output having a controllable pulse width. Systems and methods may include a delay line having a plurality of stages. A delay per stage calculation circuit is configured to determine a per-stage delay of the delay line using a first clock input. A pulse generation circuit is configured to generate the pulse output using the delay line based on the per-stage delay using a second clock input, the second clock input having a lower frequency than the first clock input.
    Type: Application
    Filed: May 6, 2021
    Publication date: August 19, 2021
    Inventors: Ruey-Bin Sheen, Ming Hsien Tsai, Chih-Hsien Chang, Tsung-Hsien Tsai
  • Publication number: 20210250041
    Abstract: A device includes a phase detector circuit, a charge pump circuit, a sample and hold circuit, a comparator, and a controller. The phase detector circuit detects a clock skew between a reference signal and an input signal. The charge pump circuit translates the clock skew into a voltage. A sample and hold circuit samples the voltage, at a first time, and maintain the sampled voltage until a second time. The comparator (i) detects a loop gain associated with the input signal based on the sampled voltage and the voltage at the second time and (ii) outputs a loop gain signal for adjustment of the input signal. The controller is coupled to the phase detector, the comparator, and the sample and hold circuit. The controller generates a plurality of control signals for automatically controlling operation of the phase detector, the comparator, and the sample and hold circuit.
    Type: Application
    Filed: December 4, 2020
    Publication date: August 12, 2021
    Inventors: Mao-Hsuan Chou, Ya-Tin Chang, Ruey-Bin Sheen, Chih-Hsien Chang
  • Publication number: 20210242862
    Abstract: Systems, methods, and devices are provided for a circuit for generating a pulse output having a controllable pulse width. Systems and methods may include a delay line having a plurality of stages. A delay per stage calculation circuit is configured to determine a per-stage delay of the delay line using a first clock input. A pulse generation circuit is configured to generate the pulse output using the delay line based on the per-stage delay using a second clock input, the second clock input having a lower frequency than the first clock input.
    Type: Application
    Filed: April 19, 2021
    Publication date: August 5, 2021
    Inventors: Ruey-Bin Sheen, Ming Hsien Tsai, Chih-Hsien Chang, Tsung-Hsien Tsai
  • Patent number: 11077217
    Abstract: The present invention provides a radioactive labeling method for neuropeptide Y (NPY) compound and a mammalian diagnostic radioactive targeting medicine with NPY peptide being modified at position 27th to 36th, and after binding with the chelating agent and labeling the radiation nucleus 66Ga67Ga68Ga177Lu or 111In to provide a radioactive targeting medicine for multi-type breast cancer diagnosis and treatment.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: August 3, 2021
    Assignee: INSTITUTE OF NUCLEAR ENERGY RESEARCH, ATOMIC ENERGY COUNCIL, EXECUTIVE YUAN
    Inventors: Ming-Hsin Li, Su-Jung Chen, Ming-Wei Chen, Yuan-Ruei Huang, Shih-Ying Lee, Chun-Fang Feng, Sheng-Nan Lo, Chih-Hsien Chang
  • Publication number: 20210226584
    Abstract: Oscillators and methods for realignment of an oscillator are provided. An oscillator includes an inductor having first and second terminals and a capacitor electrically coupled in parallel to the inductor at the first and second terminals. A first transistor of a first conductivity type is electrically coupled to the first terminal and a voltage source. The first transistor includes a gate configured to receive a first realignment signal. When the first realignment signal is in a realignment state, the first transistor is turned on and a voltage of the first terminal is increased from a low level to a high level in order to align a phase of a waveform of the oscillator.
    Type: Application
    Filed: December 14, 2020
    Publication date: July 22, 2021
    Inventors: Tsung-Hsien Tsai, Ruey-Bin Sheen, Chih-Hsien Chang, Cheng-Hsiang Hsieh
  • Publication number: 20210173009
    Abstract: An apparatus and method for providing a phase noise built-in self test (BIST) circuit are disclosed herein. In some embodiments, a method and apparatus for forming a multi-stage noise shaping (MASH) type high-order delta sigma (??) time-to-digital converter (TDC) are disclosed. In some embodiments, an apparatus includes a plurality of first-order ?? TDCs formed in an integrated circuit (IC) chip, wherein each of the first-order ?? DCs are connected to one another in a MASH type configuration to provide the MASH type high-order ?? TDC, wherein the MASH type high-order ?? TDC is configured to measure the phase noise of a device under text (DUT).
    Type: Application
    Filed: February 19, 2021
    Publication date: June 10, 2021
    Inventors: Mao-Hsuan CHOU, Ya-Tin Chang, Ruey-Ben Sheen, Chih-Hsien Chang
  • Patent number: 11031927
    Abstract: Systems, methods, and devices are provided for a circuit for generating a pulse output having a controllable pulse width. Systems and methods may include a delay line having a plurality of stages. A delay per stage calculation circuit is configured to determine a per-stage delay of the delay line using a first clock input. A pulse generation circuit is configured to generate the pulse output using the delay line based on the per-stage delay using a second clock input, the second clock input having a lower frequency than the first clock input.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: June 8, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ruey-Bin Sheen, Ming Hsien Tsai, Chih-Hsien Chang, Tsung-Hsien Tsai
  • Publication number: 20210167784
    Abstract: A frequency divider circuit includes a counter configured to generate a counter signal responsive to a frequency of a clock signal and a frequency ratio, and a compensation circuit coupled to the counter, and configured to generate an output signal. The output signal has a frequency equal to the frequency of the clock signal divided by a frequency ratio, and a duty cycle lower than 50% and greater than 1/r, where r is the frequency ratio.
    Type: Application
    Filed: February 9, 2021
    Publication date: June 3, 2021
    Inventors: Mao-Hsuan CHOU, Ruey-Bin SHEEN, Chih-Hsien CHANG
  • Patent number: 10965293
    Abstract: A delay-locked loop includes a phase detector configured to detect a phase difference between a first clock and a second clock, a charge pump configured to increase a charge amount at a capacitive load in accordance with a first charge amount and decrease the charge amount at the capacitive load in accordance with a second charge amount based on a phase difference provided by the phase detector, a sample and hold circuit configured to receive the charge amount from the capacitive load and hold the charge amount, and a voltage control delay line configured to select a delay amount based on the charge amount received from the sample and hold circuit. At least one parameter of the delay-locked loop is configured such that a desired pump current ratio of a delay cell is achieved by adjusting a delay amount of the delay cell and/or an amount of current coupled to the delay cell.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: March 30, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ya-Tin Chang, Chih-Hsien Chang, Mao-Hsuan Chou, Ruey-Bin Sheen