Patents by Inventor Chih-Hsien Chang

Chih-Hsien Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200301289
    Abstract: A method includes receiving a layout that includes a shape to be formed on a photomask and determining a plurality of target lithographic contours for the shape, wherein the plurality of target lithographic contours includes a first target lithographic contour for a first set of process conditions and a second target lithographic contour for a second set of process conditions, performing a lithographic simulation of the layout to produce a first simulated contour at the first set of process conditions and a second simulated contour at the second set of process conditions, determining a first edge placement error between the first simulated contour and the first target lithographic contour and a second edge placement error between the second simulated contour and the second target lithographic contour, and determining a modification to the layout based on the first edge placement error and the second edge placement error.
    Type: Application
    Filed: June 8, 2020
    Publication date: September 24, 2020
    Inventors: Dong-Yo Jheng, Ken-Hsien Hsieh, Shih-Ming Chang, Chih-Jie Lee, Shuo-Yen Chou, Ru-Gun Liu
  • Publication number: 20200303316
    Abstract: A package structure includes a redistribution layer (RDL) structure, a die, and an encapsulant. The die is attached to the RDL structure through an adhesive layer. The encapsulant is disposed on the RDL structure and laterally encapsulates the die and the adhesive layer. The encapsulant includes a protruding part extending into the RDL structure and having a bottom surface in contact with the RDL structure.
    Type: Application
    Filed: June 10, 2020
    Publication date: September 24, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Hao Chang, Hao-Yi Tsai, Tsung-Hsien Chiang, Tin-Hao Kuo
  • Patent number: 10784872
    Abstract: Systems, methods, and devices for fractional realignment are disclosed herein. A feedback divider generates a feedback dividing clock signal based on a controlling oscillator frequency. A delta-sigma modulator is coupled to the feedback divider and generates a dividing ratio to the feedback divider. An accumulating phase adjustor is coupled to the delta-sigma modulator and (i) determines a difference between a frequency tuning word (FCW) and the dividing ratio and (ii) generates a coarse tuning word and a fine tuning word. A digital-to-time converter (DTC) is coupled to the accumulating phase adjustor and generates a first clock frequency based on a reference clock frequency, the coarse tuning word and the fine tuning word. A realignment pulse generator is coupled to the DTC and generates a realignment clock based on the first clock frequency having a period that is the same as a period of the controlling oscillator frequency.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: September 22, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Tsung-Hsien Tsai, Ruey-Bin Sheen, Chih-Hsien Chang, Cheng-Hsiang Hsieh
  • Publication number: 20200286738
    Abstract: A method includes forming a first layer on a substrate; forming a first plurality of trenches in the first layer by a patterning process; and forming a second plurality of trenches in the first layer by another patterning process, resulting in combined trench patterns in the first layer. A first trench of the second plurality connects two trenches of the first plurality. The method further includes forming dielectric spacer features on sidewalls of the combined trench patterns. A space between two opposing sidewalls of the first trench is completely filled by the dielectric spacer features and another space between two opposing sidewalls of one of the two trenches is partially filled by the dielectric spacer features.
    Type: Application
    Filed: May 22, 2020
    Publication date: September 10, 2020
    Inventors: RU-GUN LIU, CHENG-HSIUNG TSAI, CHUNG-JU LEE, CHIH-MING LAI, CHIA-YING LEE, JYU-HORNG SHIEH, KEN-HSIEN HSIEH, MING-FENG SHIEH, SHAU-LIN SHUE, SHIH-MING CHANG, TIEN-I BAO, TSAI-SHENG GAU
  • Patent number: 10756083
    Abstract: A device includes a capacitive element that is coupled between first and second nodes and that includes a first well region, a second well region, and a transistor. The second well region is formed in the first well region, has a different conductivity type than the first well region, and is coupled to the second node. The transistor includes source and drain regions formed in the second well region and coupled to each other and to the second node, a channel region between the source and drain regions, and a gate region over the channel region. The first well region and the gate region are coupled to each other and to the first node, whereby a capacitance of the capacitive element is increased without substantially enlarging a physical size of the capacitive element.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: August 25, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yu-Tso Lin, Chih-Hsien Chang, Min-Shueh Yuan, Robert Bogdan Staszewski, Seyednaser Pourmousavian
  • Patent number: 10749537
    Abstract: Hybrid phase lock loop (PLL) devices are provided that combine advantages of the digital controlled loop and the analog controlled loop. For example, a hybrid PLL includes a digital controlled loop that receives a reference input signal and an output signal of the hybrid PLL, and generates a digital tuning word. The hybrid PLL further includes an analog controlled loop that receives the reference input signal and the output signal of the hybrid PLL, and generates an output voltage. The hybrid PLL also includes a hybrid oscillator. An oscillator controller of the digital controlled loop controls the hybrid oscillator using the digital tuning word and disables the analog controlled loop during a frequency tracking operational mode of the hybrid PLL. The oscillator controller enables the analog controlled loop to control the hybrid oscillator during the phase tracking operational mode of the hybrid PLL.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: August 18, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Hsien Tsai, Chih-Hsien Chang, Ruey-Bin Sheen, Cheng-Hsiang Hsieh
  • Patent number: 10743433
    Abstract: An apparatus is disclosed that comprises a first structure configured to be connected to a chassis, a second structure configured to be attached to the first structure, the second structure including at least one first connector and a damper disposed between the first structure and the second structure, the damper configured to allow the second structure to move in one dimension relative to the first structure when the first connector is moved in a direction to be coupled to a second connector that is not aligned with the first connector.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: August 11, 2020
    Assignee: DELL PRODUCTS L.P.
    Inventors: Chih Hsien Chang, Yi Chang Chen
  • Publication number: 20200237938
    Abstract: The present invention provides a radioactive labeling method for neuropeptide Y (NPY) compound and a mammalian diagnostic radioactive targeting medicine with NPY peptide being modified at position 27th to 36th, and after binding with the chelating agent and labeling the radiation nucleus 66Ga, 67Ga, 68Ga, 177Lu or 111In to provide a radioactive targeting medicine for multi-type breast cancer diagnosis and treatment.
    Type: Application
    Filed: December 11, 2018
    Publication date: July 30, 2020
    Inventors: Ming-Hsin Li, Su-Jung Chen, Ming-Wei Chen, Yuan-Ruei Huang, Shih-Ying Lee, Chun-Fang Feng, Sheng-Nan Lo, Chih-Hsien Chang
  • Patent number: 10723841
    Abstract: A method for preparing a compound and a method for preparing a polymer employing the same are provided. The method for preparing a compound includes reacting a compound having a structure represented by Formula (I) with a compound having a structure represented by Formula (III) in the presence of a compound having a structure represented by Formula (II) to obtain a compound having a structure represented by Formula (IV) wherein Ar1 is substituted or unsubstituted aryl group; X is —O—, —S—, or —NH—; R1 is independently hydrogen or C1-6 alkyl group; R2 is hydroxyl group, C1-6 alkyl group, phenyl group, or tolyl group; and R3 is independently C1-6 alkyl group, C5-8 cycloalkyl group, or C2-6 alkoxyalkyl group.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: July 28, 2020
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH
    Inventors: Po-Hsien Ho, Chih-Hsiang Lin, Feng-Jen Tsai, Cheng-Hsing Fan, Yih-Her Chang, Hsin-Ching Kao, Chien-Ming Chen
  • Publication number: 20200225551
    Abstract: A reflective display device includes a thin-film transistor (TFT) array substrate, a front panel laminate (FPL), a front protection sheet, a back protection sheet, a light blocking layer, and a light source. The front panel laminate is located on the TFT array substrate, and has a transparent conductive layer and a display medium layer. The display medium layer is located between the transparent conductive layer and the TFT array substrate. The front protection sheet is located on the front panel laminate. The back protection sheet is located below the TFT array substrate. The light blocking layer at least covers a lateral surface of the back protection sheet. The light source faces toward a lateral surface of the front panel laminate, a lateral surface of the TFT array substrate, and the lateral surface of the back protection sheet.
    Type: Application
    Filed: July 24, 2019
    Publication date: July 16, 2020
    Inventors: Chia-Chi CHANG, Chih-Chun CHEN, Chi-Ming WU, Yi-Ching WANG, Jia-Hung CHEN, Cheng-Hsien LIN
  • Patent number: 10700008
    Abstract: A package structure and a method of manufacturing the same are provided. The package structure includes a die, a RDL structure, an encapsulant and a conductive terminal. The die is on a redistribution layer (RDL) structure. The RDL structure comprises a polymer layer and a RDL in the polymer layer. The encapsulant is on the RDL structure and laterally aside the die. The encapsulant comprises a body part and an extending part underlying the body part. The conductive terminal is electrically connected to the RDL structure and the die. The body part of the encapsulant encapsulates sidewalls of the die. The extending part of the encapsulant extends into the polymer layer.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: June 30, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Hao Chang, Hao-Yi Tsai, Tsung-Hsien Chiang, Tin-Hao Kuo
  • Publication number: 20200195148
    Abstract: A power conversion system comprises a plurality of power converter modules, each including a bi-directional DC to DC converter and a current controller, wherein the bi-directional DC to DC converter is connected to the current controller, for charging or discharging a DC power source according to a distribution command received from the current controller, and a voltage controller, connecting to the plurality of power converter modules, for generating a current command to the current controller, wherein the voltage controller generates a current command to the current controller of the power converter module according to the detected capacity and voltage of the DC power source, whereby the current controller generates the distribution command to the bi-directional DC to DC converter with the received current command.
    Type: Application
    Filed: December 17, 2018
    Publication date: June 18, 2020
    Inventors: Shu-Hsien Wen, Chih-Hsien Chung, Jin-Kuan Chang
  • Patent number: 10678142
    Abstract: Various examples of a technique for performing optical proximity correction and for forming a photomask are provided herein. In some examples, a layout is received that includes a shape to be formed on a photomask. A plurality of target lithographic contours are determined for the shape that includes a first target contour for a first set of process conditions and a second target contour that is different from the first target contour for a second set of process conditions. A lithographic simulation of the layout is performed to produce a first simulated contour at the first set of process conditions and a second simulated contour at the second set of process conditions. A modification to the layout is determined based on edge placement errors between the first simulated contour and the first target contour and between the second simulated contour and the second target contour.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: June 9, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Dong-Yo Jheng, Ken-Hsien Hsieh, Shih-Ming Chang, Chih-Jie Lee, Shuo-Yen Chou, Ru-Gun Liu
  • Patent number: 10665467
    Abstract: A method includes forming a first layer on a substrate; forming a first plurality of trenches in the first layer by a first patterning process; and forming a second plurality of trenches in the first layer by second patterning process, wherein a first trench of the second plurality merges with two trenches of the first plurality to form a continuous trench. The method further includes forming spacer features on sidewalls of the first and second pluralities of trenches. The spacer features have a thickness. A width of the first trench is equal to or less than twice the thickness of the spacer features thereby the spacer features merge inside the first trench.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: May 26, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ru-Gun Liu, Cheng-Hsiung Tsai, Chung-Ju Lee, Chih-Ming Lai, Chia-Ying Lee, Jyu-Horng Shieh, Ken-Hsien Hsieh, Ming-Feng Shieh, Shau-Lin Shue, Shih-Ming Chang, Tien-I Bao, Tsai-Sheng Gau
  • Publication number: 20200161756
    Abstract: An electronic package structure is provided, including a substrate with an electronic component, an antenna element and a shielding element disposed on the substrate. The shielding element is positioned between the antenna element and the electronic component to prevent electromagnetic interference (EMI) from occurring between the antenna element and the electronic component. A method for fabricating the electronic package structure is also provided.
    Type: Application
    Filed: January 23, 2020
    Publication date: May 21, 2020
    Inventors: Chih-Yuan Shih, Chih-Hsien Chiu, Yueh-Chiung Chang, Tsung-Li Lin, Chi-Pin Tsai, Chien-Cheng Lin, Tsung-Hsien Tsai, Heng-Cheng Chu, Ming-Fan Tsai
  • Patent number: 10644869
    Abstract: A phase lock loop (PLL), such as an all digital phase lock loop (ADPLL) to provide an example, of the present disclosure operates in a frequency tracking mode to adjust a frequency of the output signal to be proportional to a frequency of a reference input signal, or, in a phase tracking mode to adjust a phase of the output signal to match any variations in the reference input signal. The ADPLL includes a phase and/or frequency detector that provides an error signal representing a difference, in frequency and/or phase, between the output signal and the reference input signal. The ADPLL monitors a trend of the error signal, such as a positive trend, a negative trend, or a flat trend to provide some examples, and switches among the frequency tracking mode and the phase tracking mode upon detecting a change in the trend of the error signal.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: May 5, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Hsien Tsai, Chih-Hsien Chang
  • Publication number: 20200132764
    Abstract: An apparatus and method for providing a phase noise built-in self test (BIST) circuit are disclosed herein. In some embodiments, a method and apparatus for forming a multi-stage noise shaping (MASH) type high-order delta sigma (??) time-to-digital converter (TDC) are disclosed. In some embodiments, an apparatus includes a plurality of first-order ?? TDCs formed in an integrated circuit (IC) chip, wherein each of the first-order ?? TDCs are connected to one another in a MASH type configuration to provide the MASH type high-order ?? TDC, wherein the MASH type high-order ?? TDC is configured to measure the phase noise of a device under text (DUT).
    Type: Application
    Filed: September 18, 2019
    Publication date: April 30, 2020
    Inventors: Mao-Hsuan Chou, Ya-Tin Chang, Ruey-Bin Sheen, Chih-Hsien Chang
  • Publication number: 20200129646
    Abstract: A radioactive labeled long-acting peptide-targeting pharmaceutical and production method, in which the peptide targeted pharmaceutical is firstly dissolved in a solution, followed by labeling the radioactive at a high temperature, and the dosage of the pharmaceutical with radioactive labeling is expected to be reduced and labeling efficiency is improved, and no further purification by filtration is required, which shortens the preparation process and reduces personnel exposure in the working environment. The radioactive labeled long-acting peptide-targeting pharmaceutical can increase the specific binding capacity of tumors and reduce the non-specific accumulation in normal tissues. It can be applied to the field of tumor and nuclear medicine for diagnosis and treatment of tumors and/or tumor metastases with efficacy and precision treatment.
    Type: Application
    Filed: October 31, 2018
    Publication date: April 30, 2020
    Inventors: Ming-Hsin Li, Chih-Hsien Chang, Su-Jung Chen, Shih-Ying Lee, Sheng-Nan Lo, Ming-Wei Chen, Yuan-Ruei Huang, Chun-Fang Feng, Shih-Wei Lo, Cheng-Hui Chuang
  • Publication number: 20200135806
    Abstract: A semiconductor device includes a substrate; a memory array over the substrate, the memory array including first magnetic tunnel junctions (MTJs), where the first MTJs are in a first dielectric layer over the substrate; and a resistor circuit over the substrate, the resistor circuit including second MTJs, where the second MTJs are in the first dielectric layer.
    Type: Application
    Filed: September 4, 2019
    Publication date: April 30, 2020
    Inventors: Tai-Yen Peng, Tsung-Hsien Chang, Yu-Shu Chen, Chih-Yuan Ting, Jyu-Horng Shieh, Chung-Te Lin
  • Publication number: 20200127671
    Abstract: A frequency divider circuit includes a counter configured to generate a counter signal responsive to a frequency of a clock signal and a frequency ratio, and a compensation circuit coupled to the counter, and configured to generate an output signal. The output signal has a frequency equal to the frequency of the clock signal divided by a frequency ratio, and a duty cycle greater than 1/r, where r is the frequency ratio.
    Type: Application
    Filed: October 9, 2019
    Publication date: April 23, 2020
    Inventors: Mao-Hsuan CHOU, Chih-Hsien CHANG, Ruey-Bin SHEEN