Abstract: The present disclosure provides a system of measuring capacitance of a device-under-test (DUT). The system includes first switch, second switch, and a capacitance measurement device. The first switch is configured to receive a supply voltage. The first and second switches are electrically connected to the DUT. The capacitance measurement device is configured to provide a first pair of non-overlapping periodic signals with a first frequency, and a second pair of non-overlapping periodic signals with a second frequency. The second frequency is ? times the first frequency. When the first switch and the second switch receive the first pair of non-overlapping periodic signals, a first current is transmitted through the first switch and the second switch. When the first switch and the second switch receive the second pair of non-overlapping periodic signals, a second current is transmitted through the first switch and the second switch.

Abstract: In some embodiments, an image sensor is provided. The image sensor includes a photodetector disposed in a semiconductor substrate. A wave guide filter having a substantially planar upper surface is disposed over the photodetector. The wave guide filter includes a light filter disposed in a light filter grid structure. The light filter includes a first material that is translucent and has a first refractive index. The light filter grid structure includes a second material that is translucent and has a second refractive index less than the first refractive index.

Abstract: A method includes receiving a layout for fabricating a mask, determining a plurality of target contours corresponding to a plurality of sets of lithographic process conditions, determining a modification to the layout, simulating the modification to the layout under the plurality of sets of lithographic process conditions to produce a plurality of simulated contours, determining a cost of the modification to the layout based on comparisons between the plurality of simulated contours and corresponding ones in the plurality of target contours, and providing the modification to the layout for fabricating the mask based at least in part on the cost being within a predetermined threshold.

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric capping structure is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.

Abstract: The present disclosure for wafer bonding, including forming an epitaxial layer on a top surface of a first wafer, forming a sacrificial layer over the epitaxial layer, trimming an edge of the first wafer, removing the sacrificial layer, forming an oxide layer over the top surface of the first wafer subsequent to removing the sacrificial layer, and bonding the top surface of the first wafer to a second wafer.

Abstract: The present disclosure provides a system of measuring capacitance of a device-under-test (DUT). The system includes first switch, second switch, and a capacitance measurement device. The first switch is configured to receive a supply voltage. The first and second switches are electrically connected to the DUT. The capacitance measurement device is configured to provide a first pair of non-overlapping periodic signals with a first frequency, and a second pair of non-overlapping periodic signals with a second frequency. The second frequency is ? times the first frequency. When the first switch and the second switch receive the first pair of non-overlapping periodic signals, a first current is transmitted through the first switch and the second switch. When the first switch and the second switch receive the second pair of non-overlapping periodic signals, a second current is transmitted through the first switch and the second switch.

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric capping structure is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.

Abstract: An electrical connector assembly includes an upper connector unit and a lower connector unit in a vertical direction. Each connector unit includes a contact module received within an insulative housing. The contact module includes an upper contact unit and a lower contacts unit stacked with each other. Each of the upper contact unit and the lower contact unit includes a front/outer contact part and a rear/inner contact part each including a plurality contacts essentially composed of a plurality of differential-pair signal contacts and a plurality of grounding contacts alternately arranged with each other in a the transverse direction wherein the differential-pair signal contacts are stamped and formed from sheet metal and successively integrally formed with a plurality of insulative transverse bars via insert-molding while the grounding contacts are directly blanked from sheet metal and associated with corresponding shielding plates assembled to the insulative transverse bar.

Abstract: Implementations are directed to methods, systems, and computer-readable media for obtaining imaging data, obtaining a depth map and a scene lighting mode vector characterizing a scene lighting of the imaging data, generating edge emphasis signals by a depth edge filtering process, generating detail signals and a base signal by a joint three-dimensional (3D) spatial-depth-value filtering process, generating, from the edge emphasis signals, the detail signals, and the base signal and using the scene lighting mode vector and the depth values, depth-aware processed signals including depth-aware enhanced edge emphasis signals, depth-aware enhanced detail signals, and depth-aware converted base signal, generating, from the depth-aware processed signals, depth-aware enhanced imaging data, and providing the depth-aware enhanced imaging data for display on a display device.

Abstract: The disclosure provides a digital-to-analog conversion device and an operation method thereof. The digital-to-analog conversion device includes a digital-to-analog conversion circuit and a slew rate enhancement circuit. The digital-to-analog conversion circuit is configured to convert a digital code into an analog voltage. An output terminal of the digital-to-analog conversion circuit outputs the analog voltage to a load circuit. A control terminal of the slew rate enhancement circuit is coupled to the digital-to-analog conversion circuit to receive a control voltage following the analog voltage. The slew rate enhancement circuit is coupled to the output terminal of the digital-to-analog conversion circuit. The slew rate enhancement circuit enhances the slew rate at the output terminal of the digital-to-analog conversion circuit based on the control voltage.

Abstract: A display driver circuit for controlling a display panel having a plurality of light-emission diode (LED) strings includes a plurality of current regulators and a control circuit. Each of the plurality of current regulators is configured to control one of the plurality of LED strings. The control circuit, coupled to the plurality of current regulators, is configured to generate a plurality of pulses in a plurality of pulse width modulation (PWM) signals and output each of the plurality of PWM signals to a respective current regulator among the plurality of current regulators. Wherein, the plurality of pulses are scrambled.

Abstract: A display driver and a driving method thereof is disclosed. The display driver includes at least one first latch, at least one second latch, an output buffer, and a comparator. The first latch receives input data. The input terminal of the second latch is coupled to the output terminal of the first latch. The output buffer, including at least one variable current source, is coupled to the second latch. The comparator is coupled to the first latch, the second latch, and the variable current source. The comparator generates at least one control signal of the variable current source.

Abstract: A source driver includes a plurality of output terminals and a plurality of driving channels. Each of the plurality of driving channels is coupled to an output terminal among the plurality of output terminals and includes an output buffer, an output enable switch and a charge sharing circuit. The output enable switch is coupled between the output buffer and the corresponding output terminal. The charge sharing circuit is coupled to the corresponding output terminal. Wherein, the charge sharing circuits of at least two of the plurality of driving channels are commonly coupled to a charge sharing bus.

Abstract: A display driver and a driving method thereof is disclosed. The display driver includes at least one first latch, at least one second latch, an output buffer, and a comparator. The first latch receives input data. The input terminal of the second latch is coupled to the output terminal of the first latch. The output buffer, including at least one variable current source, is coupled to the second latch. The comparator is coupled to the first latch, the second latch, and the variable current source. The comparator generates at least one control signal of the variable current source.

Abstract: A driving method, for a controller in a display apparatus, is disclosed. The display apparatus includes LED strings, scan transistors, current regulators and a power converter. The driving method includes following steps. LED cathode voltages are detected on nodes between the LED strings and the current regulators. When a first LED cathode voltage corresponding to a first scanning channel is equal to a minimal operable voltage of the current regulators and a second LED cathode voltage corresponding to a second scanning channel exceeds the minimal operable voltage of the current regulators, a voltage drop over one corresponding scan transistor is increased on the second scanning channel.

Abstract: A driving method, for a controller in a display apparatus, is disclosed. The display apparatus includes LED strings, scan transistors, current regulators and a power converter. The driving method includes following steps. LED cathode voltages are detected on nodes between the LED strings and the current regulators. When a first LED cathode voltage is equal to a minimal operable voltage of the current regulators and a second LED cathode voltage exceeds the minimal operable voltage of the current regulators, a driving current flowing through the second data channel is adjusted by increasing a pulse current level of the driving current and reducing a duty cycle ratio of the driving current flowing through the second data channel.

Abstract: The disclosure provides a digital-to-analog conversion device and an operation method thereof. The digital-to-analog conversion device includes a digital-to-analog conversion circuit and a slew rate enhancement circuit. The digital-to-analog conversion circuit is configured to convert a digital code into an analog voltage. An output terminal of the digital-to-analog conversion circuit outputs the analog voltage to a load circuit. A control terminal of the slew rate enhancement circuit is coupled to the digital-to-analog conversion circuit to receive a control voltage following the analog voltage. The slew rate enhancement circuit is coupled to the output terminal of the digital-to-analog conversion circuit. The slew rate enhancement circuit enhances the slew rate at the output terminal of the digital-to-analog conversion circuit based on the control voltage.

Abstract: A connector unit includes a contact module received within an insulative housing. The contact module includes an upper contact unit and a lower contacts unit stacked with each other. Each of the upper contact unit and the lower contact unit includes a front/outer contact part and a rear/inner contact part each including plural contacts integrally formed with plural insulative transverse bars via insert-molding. The contacts include plural differential pair signal contacts and plural grounding contacts alternately arranged with each other along a transverse direction. Plural grounding bars are attached to corresponding transverse bars, respectively, wherein each grounding bar include plural tabs mechanically and electrically connecting to the corresponding grounding contacts. Each grounding bar is equipped with a plastic attachment tie bar to cooperate with a corresponding transverse bar to sandwich the grounding bar therebetween for securement.

Abstract: A display driver circuit for controlling a display panel having a plurality of light-emission diode (LED) strings includes a plurality of current regulators and a control circuit. Each of the plurality of current regulators is configured to control one of the plurality of LED strings. The control circuit, coupled to the plurality of current regulators, is configured to generate a plurality of pulses in a plurality of pulse width modulation (PWM) signals and output each of the plurality of PWM signals to a respective current regulator among the plurality of current regulators. Wherein, the plurality of pulses are scrambled.

Abstract: An electrical connector includes an insulative housing defining a front cavity for receiving and a rear cavity, a terminal assembly assembled in the rear cavity, and a ground member. The terminal assembly includes an upper terminal module, a lower terminal module sandwiching a shielding module therebetween. Said The upper terminal module includes a pair of upper ground terminals. Said The lower terminal module includes a plurality of lower ground terminals. Said The shielding module includes a metallic shielding plate. The ground member is associated with the shielding module to mechanically and electrically connect at least one of the upper ground terminals and the lower ground terminals with the shielding plate.