Abstract: The present invention relates to a pitch-variable battery fixture and a battery cell formation apparatus having the same. A pitch of clamping plates of a plurality of clamping blocks is increased by a slide actuator of the pitch-variable battery fixture, and then the clamping plates are inserted into a plurality of compartments of a battery tray. The clamping plates are urged to clamp batteries by the slide actuator. The battery tray is provided for placement of the batteries, and a compressing force is exerted for shaping the batteries during a battery cell formation. The pitch-variable battery fixture is provided for clamping batteries having different thicknesses. According to the actual thickness of each battery, the thickness of the formed battery can be shaped.

Abstract: An optical system includes a sensing assembly and a processing circuit. The sensing assembly is configured to sense light and output a sensing signal accordingly. The processing circuit is configured to analyze the sensing signal. The processing circuit is configured to output a main judgment signal to an external circuit according to the sensing signal.

Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.

Abstract: The disclosure provides a fingerprint sensor and a fingerprint sensing method thereof. The fingerprint sensor includes an optical sensing array, an analog front end circuit and an image processing circuit. The optical sensing array is configured for sequentially outputting a plurality of analog fingerprint images corresponding to a finger. The analog front end circuit is coupled to the optical sensing array. The analog front end circuit is configured for sequentially receiving and converting the plurality of analog fingerprint images into a plurality of first digital fingerprint images. The image processing circuit is coupled to the analog front end circuit. The image processing circuit is configured for sequentially superimposing the plurality of first digital fingerprint images to generate an enhanced fingerprint image.

Abstract: The disclosure provides a fingerprint sensor and a fingerprint sensing method thereof. The fingerprint sensor includes an optical sensing array, an analog front end circuit and an image processing circuit. The optical sensing array is configured for sequentially outputting a plurality of analog fingerprint images corresponding to a finger. The analog front end circuit is coupled to the optical sensing array. The analog front end circuit is configured for sequentially receiving and converting the plurality of analog fingerprint images into a plurality of first digital fingerprint images. The image processing circuit is coupled to the analog front end circuit. The image processing circuit is configured for sequentially superimposing the plurality of first digital fingerprint images to generate an enhanced fingerprint image.

Abstract: A method of managing power consumption of a network interface is provided. The method is capable of cutting off the power and the clock signal supply to the MAC and the PHY receiving terminals of the network interface when the user disables the wake-up function, and when the user enables the wake-up function, the power and the clock signal are supplied to the receiver of the medium access control unit and the receiver of the physical layer unit.

Abstract: A method for coordinating packet transmission order for a plurality of registers of different priority levels is disclosed. Packets are transmitted from the registers according to the priority levels in a normal condition. A count value is generated in response to the transmitted packets. A particular priority level of one of the registers, from which a packet is being transmitted out, is recorded when the count value is larger than a predetermined threshold. Then the normal condition switches into a cleaning condition, and one packet is transmitted from each of the registers which are not empty and have priority levels lower than the particular priority level according to priority. Finally, reset the count value, and return to the normal condition. A device for coordinating packet transmission order for a plurality of registers of different priority levels is also disclosed.

Abstract: A packet receiving-transmitting method is provided for use on a packet-switching network, such as Ethernet, for the purpose of handling packets more efficiently than the prior art. By this method, each received packet is stored in a packet buffer of a fixed size and associated with just one descriptor. Based on a threshold logical segmentation size determined by the network protocol, each packet buffer is partitioned into a plurality of segments, each having an ending point linked to an Early Receive/Transmit interrupt signal with the ending point of the packet buffer being linked to an OK interrupt signal. In response to each Early Receive/Transmit interrupt signal, the packet data stored are retrieved and forwarded; and in response to the OK interrupt signal, all the remaining packet data in the packet buffer are retrieved and forwarded. After this a write-back operation is performed on the associated descriptor so as to reset the descriptor to unused status.

Abstract: A method of configuring a computer system capable of being woken up on a LAN A core power is actuated for an interval by performing a Pre-Advanced Configuration and Power Interface (Pre-ACPI) routine. Next, a PCI clock signal is retrieved in the fixed interval and then an Ethernet ID is loaded using the PCI clock signal, so as to set a south bridge to a standby mode capable of receiving a wake-up event. As a result, use of an oscillator in conventional methods can be reduced, and the computer system can be configured to be capable of being woken-up on LAN, without requiring the start-up procedure, so that the computer system may be awoken on the LAN even after an abnormal shutdown.

Abstract: A method of managing power consumption of a network interface is provided. The method is capable of cutting off the power and the clock signal supply to the MAC and the PHY receiving terminals of the network interface when the user disables the wake-up function, and when the user enables the wake-up function, the power and the clock signal are supplied to the receiver of the medium access control unit and the receiver of the physical layer unit.

Abstract: A device for verifying frequency of a clock signal generated from a clock signal generator includes a reference signal generator, a frequency divider and a comparative detector. A reference clock signal and a reset signal are provided by the reference signal generator. The frequency divider in communication with the reference signal generator and the clock signal generator receives and frequency-divides the clock signal into a bi-level divided clock signal in response to the reset signal. Then the comparative detector in communication with the frequency divider and the reference signal generator detects a level of the bi-level divided clock signal in response to the reset signal and the reference clock signal, and verifies frequency of the clock signal according to a period deviation range Te when the bi-level divided clock signal is detected to be a first level from the first to the (p?q)th detected points but a second level at the (p+1)th detected point.

Abstract: A device for verifying frequency of a clock signal generated from a clock signal generator includes a reference signal generator, a frequency divider and a comparative detector. A reference clock signal and a reset signal are provided by the reference signal generator. The frequency divider in communication with the reference signal generator and the clock signal generator receives and frequency-divides the clock signal into a bi-level divided clock signal in response to the reset signal. Then the comparative detector in communication with the frequency divider and the reference signal generator detects a level of the bi-level divided clock signal in response to the reset signal and the reference clock signal, and verifies frequency of the clock signal according to a period deviation range Te when the bi-level divided clock signal is detected to be a first level from the first to the (p−q)th detected points but a second level at the (p+1)th detected point.

Abstract: A circuit and a method for generating a variable delay clock without glitches are provided. A DLL clock output circuit comprises a selection circuit. A plurality of select signals selectively switch the corresponding clock delay lines to be the output signal by the selection circuit. Each of the select signals traverses through a delay switching circuit to adaptively delay the time points at which the select signals switch the clock delay lines to the output signal, so as to produce a glitchless variable delay clock signal.

Abstract: A wireless local area network access controller for receiving a first frame signal complying with a first format includes a conversion circuit for retrieving a second frame signal complying with a second format according to the first frame signal complying with the first format and for retrieving an access control signal. The wireless local area network access controller also includes an access circuit for processing the second frame signal complying with the second format. The wireless local area network access controller is capable of performing a hardware control according to the access control signal.

Abstract: A method for initializing an add-on card of a computer and a control chip capable of coupling with the add-on card is provided, wherein the chip has thereon a shadow register, the add-on card has thereon a configuration read-only memory. The method includes steps of loading basic configuration data stored in the configuration read-only memory and required for the operation of the chip to the chip, and storing the basic configuration data in the shadow register when a basic input/output system (BIOS) performs a configuration-data reading action from the configuration read-only memory, and initializing the chip in response to the basic configuration data.

Abstract: A method for coordinating packet transmission order for a plurality of registers of different priority levels is disclosed. Packets are transmitted from the registers according to the priority levels in a normal condition. A count value is generated in response to the transmitted packets. A particular priority level of one of the registers, from which a packet is being transmitted out, is recorded when the count value is larger than a predetermined threshold. Then the normal condition switches into a cleaning condition, and one packet is transmitted from each of the registers which are not empty and have priority levels lower than the particular priority level according to priority. Finally, reset the count value, and return to the normal condition. A device for coordinating packet transmission order for a plurality of registers of different priority levels is also disclosed.

Abstract: A circuit and a method for generating a variable delay clock without glitches are provided. A DLL clock output circuit comprises a selection circuit. A plurality of select signals selectively switch the corresponding clock delay lines to be the output signal by the selection circuit. Each of the select signals traverses through a delay switching circuit to adaptively delay the time points at which the select signals switch the clock delay lines to the output signal, so as to produce a glitchless variable delay clock signal.

Abstract: A method of configuring a computer system capable of being woken up on LAN is disclosed. The method firstly actuates a core power for an interval by performing a Pre-Advanced Configuration and Power Interface (Pre-ACPI) routine. Next, the method retrieves a PCI clock signal in the fixed interval and then loads an Ethernet ID using the PCI clock signal, so as to set a south bridge to a standby mode capable of receiving a wake-up event. The invention can reduce an oscillator used in the conventional methods, and be capable of being woken-up on LAN without requiring the start-up procedure. And the invention can further solve the problem associated with the conventional methods, wherein an abnormal shutdown renders the computer system incapable of being woken up on LAN.

Abstract: A method and system of testing a chip for testing a circuit module in the chip. The system is integrated into the chip. The reference clock and the test command are sent to the testing system serially. The testing system, in response to the test command, performs test actions on the circuit module, producing a test result. The test result is serially sent to the test machine.

Abstract: A method and system of testing a chip for testing a circuit module in the chip. The system is integrated into the chip. The reference clock and the test command are sent to the testing system serially. The testing system, in response to the test command, performs test actions on the circuit module, producing a test result. The test result is serially sent to the test machine.