Abstract: A method and system of testing a chip for testing a circuit module in the chip. The system is integrated into the chip. The reference clock and the test command are sent to the testing system serially. The testing system, in response to the test command, performs test actions on the circuit module, producing a test result. The test result is serially sent to the test machine.

Abstract: A protecting apparatus for protecting an isolation circuit between different power domains receives a first signal, which is a level-changeable signal, from a first power domain and outputs a second signal to the isolation circuit. The apparatus includes an anti-noise circuit and a signal shaper. The anti-noise circuit receives the first signal. The signal shaper receives the output of the anti-noise circuit and outputs the second signal to the isolation circuit.

Abstract: A packet receiving-transmitting method is provided for use on a packet-switching network, such as Ethernet, for the purpose of handling packets more efficiently than the prior art. By this method, each received packet is stored in a packet buffer of a fixed size and associated with just one descriptor. Based on a threshold determined by the network protocol, each packet buffer is partitioned into a plurality of segments, each having an ending point linked to an Early Receive/Transmit interrupt signal with the ending point of the packet buffer being linked to an OK interrupt signal. In response to each Early Receive/Transmit interrupt signal, the packet data stored are retrieved and forwarded; and in response to the OK interrupt signal, all the remaining packet data in the packet buffer are retrieved and forwarded. After this a write-back operation is performed on the associated descriptor so as to reset the descriptor to unused status.