Abstract: A testing device includes a transfer interface, a tester, a first socket group and a second socket group. The first socket group includes a plurality of tested devices coupled in series and the second socket group includes a plurality of tested devices coupled in series. The tester is electrically connected to the socket group via the transfer interface. The transfer interface is configured to merge a first testing signal with a second testing signal to generate a double frequency testing signal. The double-frequency testing signal and a plurality of control signals are provided to the tested devices in the first socket group and the second socket group to perform the testing procedure on the tested devices of a same tested device pair simultaneously, and performing the testing procedure on the tested device pairs sequentially.

Abstract: The communication interface including a data encoder. The data encoder receives a data package which has at least one first output signal with N bits, generates and outputs at least one transmitting signal during one period of a reference clock signal and determining a voltage level of the transmitting signal according to a logic value of the first output signal, wherein N is an integer larger than 1.

Abstract: A testing device includes a transfer interface, a tester, a first socket group and a second socket group. The first socket group includes a plurality of tested devices coupled in series and the second socket group includes a plurality of tested devices coupled in series. The tester is electrically connected to the socket group via the transfer interface. The transfer interface is configured to merge a first testing signal with a second testing signal to generate a double frequency testing signal. The double-frequency testing signal and a plurality of control signals are provided to the tested devices in the first socket group and the second socket group to perform the testing procedure on the tested devices of a same tested device pair simultaneously, and performing the testing procedure on the tested device pairs sequentially.

Abstract: A testing device of high-frequency memory comprises a transfer interface, a tester and a socket group. The tester is electrically connected to the socket group via the transfer interface. The transfer interface is configured to merge a first testing signal with a second testing signal to generate a double frequency testing signal, wherein the first testing signal and the second testing signal are outputted by the tester, and through the transfer interface, the double frequency testing signal is shared and transmitted to the socket group for testing at least two memory packages disposed on the socket group.

Abstract: A testing device of high-frequency memory comprises a transfer interface, a tester and a socket group. The tester is electrically connected to the socket group via the transfer interface. The transfer interface is configured to merge a first testing signal with a second testing signal to generate a double frequency testing signal, wherein the first testing signal and the second testing signal are outputted by the tester, and through the transfer interface, the double frequency testing signal is shared and transmitted to the socket group for testing at least two memory packages disposed on the socket group.

Abstract: Disclosed is a memory testing device having cross interconnections of multiple drivers, comprising a first wiring bus and a second wiring bus connected to a first device area and a third wiring bus and a fourth wiring bus connected to a second device area. A first I/O driver module is connected to the first wiring bus through a first driving bus. A second I/O driver module is connected to the third wiring bus through the second driving bus. The fourth wiring bus is Y-shaped connected to the node between the first wiring bus and first driving bus. And, the second wiring bus is Y-shaped connected to the node between the third wiring bus and the second driving bus.

Abstract: Disclosed is a memory testing device having cross interconnections of multiple drivers, comprising a first wiring bus and a second wiring bus connected to a first device area and a third wiring bus and a fourth wiring bus connected to a second device area. A first I/O driver module bus is connected to the first wiring bus through a first driving bus. A second I/O driver module bus is connected to the third wiring bus through the second driving bus. The fourth wiring bus is Y-shaped connected to the node between the first wiring bus and first driving bus. And, the second wiring bus is Y-shaped connected to the node between the third wiring bus and the second driving bus.

Abstract: A testing apparatus and a method for testing a semiconductor devices array, which includes a plurality of rows and a plurality of columns, are provided. The testing apparatus includes a first testing circuit and a second testing circuit. The first testing circuit connects and transmits a clock signal, an input command signal and a data signal to at least one of the rows of the semiconductor devices array. The second testing circuit connects and transmits a selecting signal to at least one of the columns of the semiconductor devices array. Between two devices in a row, a difference in arrival times of the clock signal, a difference in arrival times of the input command signal, and a difference in arrival times of the data signal are equal.

Abstract: A testing apparatus and a method for testing a semiconductor devices array, which includes a plurality of rows and a plurality of columns, are provided. The testing apparatus includes a first testing circuit and a second testing circuit. The first testing circuit connects and transmits a clock signal, an input command signal and a data signal to at least one of the rows of the semiconductor devices array. The second testing circuit connects and transmits a selecting signal to at least one of the columns of the semiconductor devices array. Between two devices in a row, a difference in arrival times of the clock signal, a difference in arrival times of the input command signal, and a difference in arrival times of the data signal are equal.

Abstract: The present invention provides a method for accessing a memory chip. The method includes: positioning a plurality of first input pins and a plurality of second input pins on the memory chip; respectively inputting a plurality of row address signals into the plurality of first input pins, where a length of a row address command package of each row address signal corresponds to a plurality of clock periods of a clock signal, and the row address command package includes a plurality of row input commands; and respectively inputting a plurality of column address signals into the plurality of second input pins, where a length of a column address command package of each column address signal corresponds to a plurality of clock periods of the clock signal, and the column address command package includes a plurality of column input commands.

Abstract: A memory module includes a plurality of memory sub-modules and a plurality of groups of input pins, where each memory module includes a plurality of memory chips and the memory chips are series-connected. In addition, the plurality of groups of input pins are connected to the plurality of memory modules, respectively, and are utilized to receive the same input signals, where each group of input pins includes a plurality of input pins which are utilized to transmit the input signals to a corresponding memory module.

Abstract: An apparatus for testing a semiconductor device is disclosed. According to the present invention, the apparatus includes a pair of input pins, a first conductive wire, a second conductive wire, a driver and a terminator. A device-under-test (DUT) is connected to one of the pair of input pins. The first conductive wire and the second conductive wire are connected in parallel between the pair of input pins. The driver is coupled to the first conductive wire via a third conductive wire, and the terminator is coupled to the second conductive wire via a fourth conductive wire.

Abstract: An apparatus for testing a semiconductor device is disclosed. According to the present invention, the apparatus includes a pair of input pins, a first conductive wire, a second conductive wire, a driver and a terminator. A device-under-test (DUT) is connected to one of the pair of input pins. The first conductive wire and the second conductive wire are connected in parallel between the pair of input pins. The driver is coupled to the first conductive wire via a third conductive wire, and the terminator is coupled to the second conductive wire via a fourth conductive wire.

Abstract: An apparatus for testing a semiconductor device is disclosed. According to the present invention, the apparatus includes a pair of input pins, a first conductive wire, a second conductive wire, a driver and a terminator. A device-under-test (DUT) is connected to one of the pair of input pins. The first conductive wire and the second conductive wire are connected in parallel between the pair of input pins. The driver is coupled to the first conductive wire via a third conductive wire, and the terminator is coupled to the second conductive wire via a fourth conductive wire.