APPARATUS AND METHOD FOR TESTING SEMICONDUCTOR DEVICE
An apparatus for testing a semiconductor device is disclosed. According to the present invention, the apparatus includes a pair of input pins, a first conductive wire, a second conductive wire, a driver and a terminator. A device-under-test (DUT) is connected to one of the pair of input pins. The first conductive wire and the second conductive wire are connected in parallel between the pair of input pins. The driver is coupled to the first conductive wire via a third conductive wire, and the terminator is coupled to the second conductive wire via a fourth conductive wire.
(a) Field of the Invention
The invention relates to an apparatus and a method for testing a high-speed semiconductor device.
(b) Description of the Prior Art
Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM) is a memory technique developed based upon SDRAM. Unlike SDRAM that is capable of only supporting one data operation during each clock period, DDR SDRAM has capability of executing two data operations during each clock period. Therefore, not only bandwidth of memory is doubled but also data transmission capacity is multiplied. For the aforesaid advantage, DDR SDRAM is extensively applied in computer system platforms including personal computers, workstations, servers, laptop computers, portable devices, computer networks, and communication products, and consequently stands as a mainstream product in memory techniques. Along with technique advancement, data rate of DDR SDRAM has increased from 200/266 MHz to 533/667 MHz, and can promisingly be further increased to 800 MHz/1.066 GHz. It is to be noted that frequency upgrading is also an arduous challenge for testing techniques.
Referring to
Referring to
Pins of each of the DUTs 26A and 26B are generally divided into input pins and input/output (I/O) pins. Referring to
It is to be noted that I/O end of DDR SDRAM are differentiated in 4-bit, 8-bit and 16-bit. Connection configuration in
Referring to
It is therefore an object of the invention to provide an apparatus and a method for testing a semiconductor device, in that a little modification is made to a prior test apparatus and the modified apparatus can then be applied for testing 4-bit, 8-bit and 16-bit I/O semiconductor devices, thereby reducing investment costs of apparatuses and equipments for memory manufacturers and test houses.
To accomplish the aforesaid object, the invention provides a semiconductor device test apparatus for testing a DUT. A test apparatus according to the invention comprises a pair of input pins, with a DUT coupled to one of the input pins; a first conductive wire coupled between the pair of input pins; a second conductive wire coupled between the pair of input pins; a driver coupled to the first conductive wire via a third conductive wire; and a terminator coupled to the second conductive wire via a fourth conductive wire.
The invention also provides a semiconductor device test apparatus for testing a DUT. A test apparatus according to the invention comprises a first I/O pin and a second I/O pin, with a DUT coupled to the first I/O pin; a bus having a plurality of conductive wires, with one of the conductive wires coupled between the first I/O pin and the second I/O pin; a driver coupled to the first I/O pin when under an input mode; a first terminator coupled to the first I/O pin when under an output mode; a comparator coupled to the second I/O pin; and a second terminal coupled to the second I/O pin when under an output mode.
BRIEF DESCRIPTION OF THE DRAWINGS
To better understand technical contents of the invention, detailed descriptions of preferred embodiments shall be given with the accompanying drawings below.
Referring to
Thus, although output ends of DDR SDRAM are differentiated as 4-bit, 8-bit and 16-bit, the input pins 67A and 67B are respectively inserted into the DUTs 26A and 26B when utilized for 4-bit or 8-bit applications; and the input pin 67A or 67B is left floating and the DUT 26B is removed as in
Referring to
Referring to
Referring to
Referring to
From the aforesaid description of the invention, although output end of DDR SDRAM are differentiated in 4-bit, 8-bit and 16-bit, the I/O pins 79A/89A and 79B/89B can be respectively inserted to the DUTs 26A and 26B when utilized for 4-bit or 8-bit applications as shown in
It is of course to be understood that the embodiments described herein are merely illustrative of the principles of the invention and that a wide variety of modifications thereto may be effected by persons skilled in the art without departing from the spirit and scope of the invention as set forth in the following claims.
Claims
1. A test apparatus for testing a device-under-test (DUT), comprising:
- a pair of input pins, with the DUT coupled to one of said input pins;
- a first conductive wire coupled between said input pins;
- a second conductive wire coupled between said input pins;
- a driver coupled to said first conductive wire via a third conductive wire, wherein a connecting point of said first conductive wire and said third conductive wire forms a first node for distinguishing said first conductive wire into a first sub conductive wire and a second sub conductive wire respectively coupled to said input pins; and
- a terminator coupled to said second conductive wire via a fourth conductive wire.
2. The test apparatus in accordance with claim 1, wherein said third conductive wire and said fourth conductive wire have substantially the same impedance.
3. (canceled)
4. The test apparatus in accordance with claim 1, wherein said first sub conductive wire and said second sub conductive wire have substantially the same impedance.
5. The test apparatus in accordance with claim 1, wherein a connecting point of said second conductive wire and said fourth conductive wire forms a second node for distinguishing said second conductive wire into a third sub conductive wire and a fourth sub conductive wire respectively coupled to said input pins.
6. The test apparatus in accordance with claim 5, wherein said third sub conductive wire and said fourth sub conductive wire have substantially the same impedance.
7. The test apparatus in accordance with claim 1, wherein said terminator has a resistor and a voltage source connected in series.
8. A test method for testing a device-under-test (DUT), comprising steps of:
- providing a pair of input pins, with the DUT coupled to one of said input pins;
- providing a first conductive wire coupled between said input pins;
- providing a second conductive wire coupled between said input pins;
- providing a driver coupled to said first conductive wire via a third conductive wire, wherein a connecting point of said first conductive wire and said third conductive wire forms a first node for distinguishing said first conductive wire into a first sub conductive wire and a second sub conductive wire respectively coupled to said input pins; and
- providing a terminator coupled to said second conductive wire via a fourth conductive wire.
9. The test method in accordance with claim 8, wherein said third conductive wire and said fourth conductive wire have substantially the same impedance.
10. (canceled)
11. The test method in accordance with claim 8, wherein said first sub conductive wire and said second sub conductive wire have substantially the same impedance.
12. The test method in accordance with claim 8, wherein a connecting point of said second conductive wire and said fourth conductive wire forms a second node for distinguishing said second conductive wire into a third sub conductive wire and a fourth sub conductive wire respectively coupled to said input pins.
13. The test method in accordance with claim 12, wherein said third sub conductive wire and said fourth sub conductive wire have substantially the same impedance.
14. A test apparatus for testing a device-under-test (DUT), comprising:
- a first I/O pin and a second I/O pin, with the DUT coupled to said first I/O pin;
- a bus having a plurality of conductive wires, one of which is coupled between said first I/O pin and said second I/O pin;
- a driver coupled to said first I/O pin under an input mode;
- a first terminator coupled to said first I/O pin under an output mode;
- a comparator coupled to said second I/O pin; and
- a second terminator coupled to said second I/O pin under said output mode.
15. The test apparatus in accordance with claim 14, further comprising a first switch coupled between said first terminator and said first I/O pin.
16. The test apparatus in accordance with claim 15, wherein said first terminator has a resistor and a voltage source connected in series.
17. The test apparatus in accordance with claim 14, further comprising a second switch coupled between said second terminator and said second I/O pin.
18. The test apparatus in accordance with claim 17, wherein said second terminator has a resistor and a voltage source connected in series.
19. A test method for testing a first DUT and a second DUT, wherein said first DUT has a first effective pin and a first ineffective pin and said second DUT has a second effective pin and a second ineffective pin, the test method comprising the following steps of:
- providing a first bus coupled between said first effective pin and said second ineffective pin; and
- providing a second bus couple between said first ineffective pin and said second effective pin;
- wherein, when said first DUT is being tested, said second ineffective pin is left floating; when said second DUT is being test, said first ineffective pin is left floating.
20. (canceled)
Type: Application
Filed: Sep 27, 2004
Publication Date: Oct 6, 2005
Inventor: Chih-Hui Yeh (Hsinchu City)
Application Number: 10/949,338