Patents by Inventor Chih-Hung Hsu

Chih-Hung Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10973647
    Abstract: An artificial joint includes a first joint assembly and a second joint assembly. The first joint assembly is adapted to be connected to a first bone and has a first contacting surface, wherein the first contacting surface includes a first convex arc surface, a second convex arc surface, and a third convex arc surface. The second joint assembly is adapted to be connected to a second bone and has a second contacting surface, wherein the second contacting surface is in contact with the first contacting surface and includes a first concave arc surface, a second concave arc surface, and a third concave arc surface, and the first concave arc surface, the second concave arc surface, and the third concave arc surface respectively correspond to the first convex arc surface, the second convex arc surface, and the third convex arc surface.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: April 13, 2021
    Assignees: Industrial Technology Research Institute, National Taiwan University Hospital
    Inventors: Pei-I Tsai, Hsin-Hsin Shen, Kuo-Yi Yang, De-Yau Lin, Yi-Hung Wen, Chih-Chieh Huang, Wei-Luan Fan, Pei-Yu Chen, Ching-Chi Hsu
  • Patent number: 10971397
    Abstract: A method of fabricating a semiconductor device includes the following steps. A substrate is provided. The substrate includes a pixel region having a first conductive region and a logic region having a second conductive region. A dielectric layer is formed on the substrate to cover the first conductive region. A first contact opening is formed in the dielectric layer to expose the first conductive region. A doped polysilicon layer is sequentially formed in the first contact opening. A first metal silicide layer is formed on the doped polysilicon layer. A second contact opening is formed in the dielectric layer to expose the second conductive region. A barrier layer and a metal layer are respectively formed in the first contact opening and the second contact opening.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: April 6, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Chia-Jung Hsu, Chun-Ya Chiu, Chin-Hung Chen, Yu-Hsiang Lin
  • Patent number: 10955120
    Abstract: A lamp has a base, a transmission mechanism, and multiple light-emitting assemblies. The transmission mechanism is mounted on the base and is rotatable around a transmission axis. The light-emitting assemblies is mounted on the base and is connected to the transmission mechanism. Each light-emitting assembly is rotatable around a rotation axis which is nonparallel with the transmission axis. The light-emitting assemblies can be rotated through driving the transmission mechanism, so as to adjust lighting effects of the light-emitting assemblies and an appearance of the lamp. Not only the lighting effects can be adjusted according to a user's need, but also the appearance of the lamp can be changed to adapt the lamp to the environment where the lamp is disposed, such that the lamp of the present invention can be widely used.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: March 23, 2021
    Assignees: RADIANT OPTO-ELECTRONICS (SUZHOU) CO., LTD., RADIANT OPTO-ELECTRONICS CORPORATION
    Inventors: Jui-Fang Wu, Pin-Tsung Wang, Pai-Ho Hsu, Chih-Hung Ju, Ming-Huang Yang
  • Patent number: 10950713
    Abstract: A mask layer is formed over a semiconductor device. The semiconductor device includes: a gate structure, a first layer disposed over the gate structure, and an interlayer dielectric (ILD) disposed on sidewalls of the first layer. The mask layer includes an opening that exposes a portion of the first layer and a portion of the ILD. A first etching process is performed to etch the opening partially into the first layer and partially into the ILD. A liner layer is formed in the opening after the first etching process has been performed. A second etching process is performed after the liner layer has been formed. The second etching process extends the opening downwardly through the first layer and through the gate structure. The opening is filled with a second layer after the second etching process has been performed.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: March 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Zhi-Chang Lin, Wei-Hao Wu, Jia-Ni Yu, Huan-Chieh Su, Ting-Hung Hsu, Chih-Hao Wang
  • Publication number: 20210067760
    Abstract: A stereoscopic display method and a system for displaying an online object are provided. The system provides a stereoscopic image server and a user-end stereoscopic image display. When a user browses a content website, the website provides a flat image to a user device, and a content server also generates a request for displaying an object. The stereoscopic image server generates a stereoscopic image data corresponding to the object according to the request. The stereoscopic image data can be obtained by querying an image database, or by calculation using a stereoscopic image resource file. The stereoscopic image data is provided for the stereoscopic image display to display a stereoscopic image. Alternatively, the stereoscopic image data can be generated by the user-end stereoscopic image display when it receives the stereoscopic image resource file from the server.
    Type: Application
    Filed: August 30, 2019
    Publication date: March 4, 2021
    Inventors: CHUN-HSIANG YANG, KAI-CHIEH CHANG, CHIH-HUNG TING, YU-CHIANG HSU
  • Publication number: 20210063869
    Abstract: A photomask includes a substrate, a multilayer stack disposed over the substrate and configured to reflect a radiation, a capping layer over the multilayer stack, and an anti-reflective layer over the capping layer. The anti-reflective layer comprises a first pattern, wherein the first pattern exposes the capping layer and is configured as a printable feature. The photomask also includes an absorber spaced apart from the printable feature from a top-view perspective.
    Type: Application
    Filed: April 15, 2020
    Publication date: March 4, 2021
    Inventors: CHIEN-HUNG LAI, HAO-MING CHANG, CHIA-SHIH LIN, HSUAN-WEN WANG, YU-HSIN HSU, CHIH-TSUNG SHIH, YU-HSUN WU
  • Patent number: 10936028
    Abstract: An electronic device and a method for controlling a fan operation are provided. A containing space of the electronic device has a fan module and a deformation sensor. The deformation sensor detects whether a fan housing of the fan module is deformed. The deformation sensor transmits a deformation signal to a controller when detecting that the fan housing is deformed. The controller drives a fan blade of the fan module to stop running after receiving the deformation signal.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: March 2, 2021
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Chih-Chin Chien, I-Feng Hsu, Ching-Chung Chen, Tse-Yang Lin, Tse-An Chu, Ching-Ya Tu, Chang-Yuan Wu, Hao-Wu Yang, Huan-Yang Yeh, Chin-Hsien Chang, Chin-Yuan Chuang, Chia-Hung Lin
  • Patent number: 10930763
    Abstract: A semiconductor device includes a first transistor and a second transistor. The first transistor includes: a first source and a first drain separated by a first distance, a first semiconductor structure disposed between the first source and first drain, a first gate electrode disposed over the first semiconductor structure, and a first dielectric structure disposed over the first gate electrode. The first dielectric structure has a lower portion and an upper portion disposed over the lower portion and wider than the lower portion. The second transistor includes: a second source and a second drain separated by a second distance greater than the first distance, a second semiconductor structure disposed between the second source and second drain, a second gate electrode disposed over the second semiconductor structure, and a second dielectric structure disposed over the second gate electrode. The second dielectric structure and the first dielectric structure have different material compositions.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: February 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Huan-Chieh Su, Zhi-Chang Lin, Ting-Hung Hsu, Jia-Ni Yu, Wei-Hao Wu, Yu-Ming Lin, Chih-Hao Wang
  • Publication number: 20210050255
    Abstract: A method of fabricating a semiconductor device includes the following steps. A substrate is provided. The substrate includes a pixel region having a first conductive region and a logic region having a second conductive region. A dielectric layer is formed on the substrate to cover the first conductive region. A first contact opening is formed in the dielectric layer to expose the first conductive region. A doped polysilicon layer is sequentially formed in the first contact opening. A first metal silicide layer is formed on the doped polysilicon layer. A second contact opening is formed in the dielectric layer to expose the second conductive region. A barrier layer and a metal layer are respectively formed in the first contact opening and the second contact opening.
    Type: Application
    Filed: September 12, 2019
    Publication date: February 18, 2021
    Applicant: United Microelectronics Corp.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Chia-Jung Hsu, Chun-Ya Chiu, Chin-Hung Chen, Yu-Hsiang Lin
  • Publication number: 20210048859
    Abstract: A circuit includes: a first interface circuit supporting multiple first interface operating modes respectively corresponding to different versions of a first data transmission protocol; a second interface circuit supporting multiple second interface operating modes respectively corresponding to different versions of a second data transmission protocol; a control circuit configured to operably instruct the first interface circuit to operate in a first target operating mode selected from the multiple first interface operating modes, and configured to operably instruct the second interface circuit to operate in a second target operating mode selected from the multiple second interface operating modes; wherein a difference between a nominal data rate of the first target operating mode and a nominal data rate of the second target operating mode is less than a predetermined threshold.
    Type: Application
    Filed: July 15, 2020
    Publication date: February 18, 2021
    Inventors: Yi Ting CHIEN, Cheng Yuan HSIAO, Chih Yu HSU, Sung Kao LIU, Wei Hung CHUANG
  • Publication number: 20210050456
    Abstract: A manufacturing method of a semiconductor device includes the following steps. An opening is formed penetrating a dielectric layer on a semiconductor substrate. A stacked structure is formed on the dielectric layer. The stacked structure includes a first semiconductor layer partly formed in the opening and partly formed on the dielectric layer, a sacrificial layer formed on the first semiconductor layer, and a second semiconductor layer formed on the sacrificial layer. A patterning process is performed for forming a fin-shaped structure including the first semiconductor layer, the sacrificial layer, and the second semiconductor layer. An etching process is performed to remove the sacrificial layer in the fin-shaped structure. The first semiconductor layer in the fin-shaped structure is etched to become a first semiconductor wire by the etching process. The second semiconductor layer in the fin-shaped structure is etched to become a second semiconductor wire by the etching process.
    Type: Application
    Filed: September 16, 2019
    Publication date: February 18, 2021
    Inventors: Chin-Hung Chen, Ssu-I Fu, Chih-Kai Hsu, Chun-Ya Chiu, Chia-Jung Hsu, Yu-Hsiang Lin
  • Publication number: 20210051248
    Abstract: An optical member driving mechanism is provided. The optical member driving mechanism includes a first portion and a matrix structure. The first portion is connected to a first optical member and corresponds to a first light. The matrix structure is disposed on the first portion and corresponds to a second light, wherein the first light is different from the second light.
    Type: Application
    Filed: January 13, 2020
    Publication date: February 18, 2021
    Inventors: Chih-Wei WENG, Juei-Hung TSAI, Shu-Shan CHEN, Mao-Kuo HSU, Sin-Jhong SONG
  • Patent number: 10909431
    Abstract: A method and a system for digital direct imaging, an image generating method and an electronic device are provided. The method for digital direct imaging includes: obtaining a first image of a first format; converting the first image into a second image of a second format, wherein the second image includes a contour description; generating a correction parameter according to at least one mark on a substrate; correcting the second image according to the contour description and the correction parameter; and performing a rasterization operation on the corrected second image and imaging the second image processed by the rasterization operation on the substrate by an exposure device.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: February 2, 2021
    Assignee: Industrial Technology Research Institute
    Inventors: Shau-Yin Tseng, Chien-Hung Lin, Yu-Sheng Lee, Yung-Chao Chen, Chih-Wei Hsu
  • Patent number: 10895007
    Abstract: An evaporation apparatus including a material source, a chamber, a passageway, and a heating component is provided. The material source is configured to provide a deposition material. The chamber includes a manifold. The passageway is configured to be connected to the material source and the manifold. The heating component is disposed in at least a portion of the passageway and configured to heat the deposition material. A calibration method of the evaporation apparatus is also provided.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: January 19, 2021
    Assignee: Industrial Technology Research Institute
    Inventors: Yu-Lin Hsu, Chien-Hung Lin, Kuo-Hsin Huang, Chao-Feng Sung, Chih-Ming Lai, Hung-Yi Chang
  • Patent number: 10883975
    Abstract: Provided is a residual toxicant detection system and a residual toxicant detection method, the residual toxicant detection method including: allowing an aqueous solution containing a residual toxicant to flow into a detection portion including a cavity; providing at a side of the cavity a light containing a specific wavelength range to react with the residual toxicant; receiving the light that passes through the cavity on another side of the cavity, thereby generating a sensing signal; and calculating an amount of change in absorbance of the aqueous solution according to the sensing signal, wherein when the amount of change in absorbance is less than a threshold value, a detection count is accumulated, and when the accumulated detection count is greater than a predetermined value, a detection result is generated. Therefore, whether or not the residual toxicant on the object is cleaned can be determined easily and accurately.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: January 5, 2021
    Assignee: Industrial Technology Research Institute
    Inventors: Chia-Jung Chang, Jui-Hung Tsai, Chih-Hao Hsu, Jing-Yuan Lin
  • Publication number: 20200395275
    Abstract: A device includes a die paddle and a plurality of leads. The leads surround the die paddle. Each of the leads includes an inner lead portion adjacent to and spaced apart from the die paddle, an outer lead portion opposite to the inner lead portion and a bridge portion between the inner lead portion and the outer lead portion. The inner lead portion has an upper bond section connected to the bridge portion and a lower support section below the upper bond section. A sum of a thickness of the upper bond section and a thickness of the lower support section is greater than a thickness of the bridge portion.
    Type: Application
    Filed: June 14, 2019
    Publication date: December 17, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Kuang-Hsiung CHEN, Chih-Hung HSU, Mei-Lin HSIEH, Yi-Cheng HSU, Yuan-Chun CHEN, Yu-Shun HSIEH, Ko-Pu WU
  • Publication number: 20200379833
    Abstract: An error handling method for a transmission interface connecting between a first device and a second device for performing data transmission between the first device and the second device, wherein a connection type between the transmission interface and the first device is a direct interface (DI) and the connection type between the transmission interface and the second device is an indirect interface (II), and the error handling method comprises: when an error is detected at the direct interface, reporting an error event to a host of the first device; when an error is detected at the indirect interface, attempting to handle the error without letting the host discover it; and when the error detected at the indirect interface is determined as unable to be solved, reporting another error event to the host.
    Type: Application
    Filed: December 12, 2019
    Publication date: December 3, 2020
    Inventors: Cheng-Yuan Hsiao, Sung-Kao Liu, Yi-Ting Chien, Wei-Hung Chuang, Chih-Yu Hsu
  • Publication number: 20200379323
    Abstract: A lens includes a casing, a first lens group, a second lens group and a heat dissipating member. The first lens group is disposed in the casing and close to a first side of the casing. The second lens group is disposed in the casing and close to a second side of the casing, wherein the first side is opposite to the second side. The heat dissipating member is disposed at the second side of the casing and contacts the casing.
    Type: Application
    Filed: April 26, 2020
    Publication date: December 3, 2020
    Inventors: Chien-Hung Lin, Tzu-Huan Hsu, Sheng-Wen Hu, Hsin-Jung Yeh, Chih-Chieh Tsung
  • Patent number: 10854502
    Abstract: A semiconductor device includes a gate structure on a fin-shaped structure, a single diffusion break (SDB) structure adjacent to the gate structure, a shallow trench isolation (STI) around the fin-shaped structure, and an isolation structure on the STI. Preferably, a top surface of the SDB structure is even with a top surface of the isolation structure, and the SDB structure includes a bottom portion in the fin-shaped structure and a top portion on the bottom portion.
    Type: Grant
    Filed: January 2, 2020
    Date of Patent: December 1, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Chun-Ya Chiu, Chi-Ting Wu, Chin-Hung Chen, Yu-Hsiang Lin
  • Publication number: 20200360287
    Abstract: A pharmaceutical composition containing a mixed polymeric micelle and a drug enclosed in the micelle, in which the mixed polymeric micelle, 1 to 1000 nm in size, includes an amphiphilic block copolymer and a lipopolymer. Also disclosed are preparation of the pharmaceutical composition and use thereof for treating cancer.
    Type: Application
    Filed: May 16, 2019
    Publication date: November 19, 2020
    Inventors: Ming-Cheng Wei, Yuan-Hung Hsu, Wen-Yuan Hsieh, Chia-Wen Huang, Chih-Lung Chen, Jhih-Yun Jian, Shian-Jy Wang