Abstract: The invention relates to new fish growth hormones, nucleic acids encoding them, and transgenic fish that express them.

Abstract: A semiconductor substrate has at least one active area and a STI surrounding the active area. An N-well and an adjacent P-well are formed in the active area. A dummy gate is formed atop the border between the N-well and the P-well, while simultaneously forming gates for other MOS transistors on the semiconductor substrate. A spacer is formed on the periphery of each gate. Finally, an N-type ion implantation process and a P-type ion implantation process are performed to form a cathode and an anode for the silicon controlled rectifier device in the P-well and the N-well between the STI and the dummy gate.

Abstract: The invention relates to new fish growth hormones, nucleic acids encoding them, and transgenic fish that express them.

Abstract: A driving device for a fluorescent tube has a high frequency oscillator which outputs a high frequency AC signal. A pulse width modulator is connected to the high frequency oscillator for outputting a PWM harmonic frequency signal. A first power switch is connected to the pulse width modulator for being turned off during a positive half-cycle of the PWM harmonic frequency signal and being turned on during a negative half-cycle of the PWM harmonic frequency signal. A second power switch is connected to the pulse width modulator for being turned on during the positive half-cycle of the PWM harmonic frequency signal and being turned off during the negative half-cycle of the PWM harmonic frequency signal. A piezoelectric transformer includes a primary winding having two input terminals connected to the first power switch and the second power switch, respectively, and a center terminal connected to the output terminal of the pulse width modulator.

Abstract: This invention provides a method for fabricating a gate conductive structure. A semiconductor substrate having a gate oxide layer thereon is provided. A conductive layer is formed on the gate oxide layer. Then, a mask layer is formed on the conductive layer. Thereafter, the mask layer and the conductive layer are patterned to form a gate mask layer and a gate conductive layer. Next, a first spacer is formed on sidewalls on the gate conductive layer and the gate mask layer, wherein the spacer is taller than the gate conductive layer. After that, the gate mask layer is removed. Then, a second spacer is formed on the gate conductive layer and adjacent to the first spacer. The second spacer is made of polysilicon so that the second spacer is conductive. Finally, a silicide layer is then formed on the surface of the second spacer and the gate conductive layer.

Abstract: A reflective/transmissive scanner having a transmissive mode light source that is synchronously moved with the image-retrieving device. The scanner is provided with a scanner body having an upper surface with slots formed therethrough and a first transparent plate disposed in an aperture in the upper surface of the scanner body on which an object to be scanned is placed. A second transparent plate is provided in the lower surface of the scanner lid, corresponding slots being formed in the second transparent plate. A first support frame is disposed within the scanner body, with a reflective light source and an image retrieving device disposed thereupon, and a second support frame is disposed within the scanner lid, with a transmissive mode light source disposed thereupon.

Abstract: A method for fabricating a two-bit flash memory cell is described in which a substrate with a trench formed therein is provided. A conformal tunnel oxide layer is then formed on the substrate, followed by forming polysilicon spacers on the portion of the tunnel oxide layer which covers the sidewalls of the trench. The polysilicon spacers are separated into a first polysilicon spacer on the right sidewall and a second polysilicon spacer on the left sidewall. Thereafter, a gate oxide layer is formed on the polysilicon spacers, followed by forming a polysilicon gate on the gate oxide layer in the substrate. Subsequently, a source/drain region is formed on both sides of the polysilicon gate in the substrate.

Abstract: A timing generating apparatus includes a master timing module adapted to receive an external reference clock and to generate a coarse timing pulse signal. A slave timing module is coupled electrically to the master timing module and receives the coarse timing pulse signal, from which a fine timing pulse signal is generated. A calibration module coupled electrically to the master timing module and the slave timing module receives the coarse timing pulse signal and the fine timing pulse signal, determines a phase difference value between the two, and generates a phase compensation signal corresponding to difference between the phase difference value and a predetermined phase difference value. The slave timing module includes a delay control unit and a voltage-controlled delay unit, which introduce a phase delay into the coarse timing pulse signal so as to generate the fine timing pulse signal.

Abstract: A method for fabricating a flash memory cell is described. A conformal ultra thin oxide layer is formed on a substrate having a trench formed therein, followed by forming silicon nitride spacers on the portion of the ultra thin oxide layer which covers the sidewalls of the trench. The silicon nitride spacers are separated into a first silicon nitride spacer on the right sidewall and a second silicon nitride spacer on the left sidewall. Thereafter, a gate oxide layer is formed on the silicon nitride spacers, followed by forming a polysilicon gate on the gate oxide layer in the substrate. Subsequently, a source/drain region is formed on both sides of the polysilicon gate in the substrate.

Abstract: A structure of an ESD protection device located between a pad and an internal circuit. The structure comprises a transistor with a source and a drain connecting to the ground, and an N+ resistor with its cross section comprising an N-well, a P-type doped region located in the N-well, and an N+ doped region located in the P-type doped region. The N+ doped region has a first terminal and a second terminal. The first terminal is connected electrically to the drain and the pad, while the second terminal is connected to the internal circuit.

Abstract: A method of fabricating flash erasable programmable read only memory. A substrate having an isolation structure is provided. A tunnel oxide layer and a floating gate layer are formed in sequence over substrate and are patterned. An ion implantation is performed and a first doped region is formed in the substrate. An oxidation step is performed to form a first oxide layer over the substrate. A nitride/oxide layer and a control gate layer are formed in sequence over the substrate. The control gate layer, the nitride/oxide layer, the first oxide layer, and the floating gate layer are patterned until the substrate is exposed. An ion implantation step is performed to form a common source region and a drain region in the substrate. Spacers are formed over the sidewalls of the control gate layer, the nitride/oxide layer, the first oxide layer, and the floating gate layer. A self-aligned silicide step is performed to form silicide layers over the control gate layer, the common source region, and the drain region.

Abstract: A method of fabricating a flash memory. A gate is formed on a provided substrate. A first doping process is performed. A patterned mask layer is formed over the substrate. A shallow trench isolation structure is formed in the substrate by using the gate and the mask layer as a mask. A portion of the substrate defined below the gate is a first active region and a portion of the substrate defined below the mask layer is a second active region. The mask layer is removed. A dielectric layer and a conductive layer are formed in sequence over the substrate. The conductive layer, the dielectric layer and the gate are patterned to form a control gate and a floating gate, wherein a portion of the control gate overlap with the second active region. A second doping process is performed.

Abstract: The present invention provides a method of fabricating a flash memory cell without silicide formation on the source regions. A liquid deposition oxide layer is formed selectively only on a common source region by using a mask layer. The liquid deposition oxide layer is formed on the common source region in order to cover the common source region. Therefore, once a salicide step is performed, a silicide layer will not form on the common source region.

Abstract: A method for forming a shallow trench isolation structure in a substrate includes the steps of forming a doped region around the future top corner regions of a trench. The concentration of dopants inside the doped region increases towards the substrate surface. Thereafter, a trench is formed in the substrate, and then a thermal oxidation operation is carried out. Utilizing the higher oxidizing rate for doped substrate relative to an undoped region, the upper corners of the trench become rounded corners. Subsequently, a liner oxide layer is formed over the substrate surface inside the trench using conventional methods. Finally, insulating material is deposited into the trench to form a trench isolation structure.

Abstract: An improved structure of a photo sensor is disclosed. Its structural feature is that a PIN photo diode is allocated in a MOSFET, by means of enlarging the detected small photo current from PIN photo diode by the MOSFET; so as to avoid the shortcoming of conventional PIN photo diode, and enhance the sensitivity of photo sensing.

Abstract: A method of reducing the fringe capacitance between a gate and a substrate in a semiconductor device. A silicon nitride is formed over a substrate with a buffer oxide layer thereon and patterned to form an opening. The buffer oxide layer within the opening is removed and another oxide layer is formed at the same place as a gate oxide layer. A poly-gate is formed at the opening with a wider width than the opening. Thus, a part of the poly-gate at both ends covers a part of the silicon nitride layer. The silicon nitride layer is then removed and leaves the poly-gate as a T-shape with two ends suspended over the substrate. With a large angle, a light dopant is implanted into the substrate under the suspended part of the poly-gate to form a lightly doped region. With another smaller angle, a heavy dopant is implanted into the substrate beside the poly-gate. Therefore, a source/drain is formed.

Abstract: A flash memory cell is fabricated by forming a lightly-doped region with only an implantation procedure to avoid lateral diffusion resulting from an increased overlap between the source region and gate as well as a short channel effect, while surrounding the source region with the lightly-doped region to thereby increase the breakdown voltage between the source region and the substrate.

Abstract: A structure of and a method for fabricating a highly sensitive photo sensor. Its structural feature is that a PIN photo diode is allocated in a MOSFET, by means of enlarging the detected small photo current from PIN photo diode by the MOSFET; so as to avoid the shortcoming of conventional PIN photo diode, and enhance the sensitivity of photo sensing.

Abstract: In a method for fabricating a ULSI MOSFET with SOI structure, an additional polysilicon layer is used to form polysilicon/metal compound metal contacts on source and drain regions and a gate so as to avoid leakage current and short channel effect problems.

Abstract: A method of fabricating an EPROM memory increases a coupling ratio and reduces lateral diffusion by forming a gate oxide layer and a coupling insulator individually. A substrate is provided with a field oxide layer to isolate a predetermined active area. A gate oxide layer is formed on the substrate. On the field oxide layer and the gate oxide layer, a polysilicon layer is deposited and defined, whereby a portion of this polysilicon layer and gate oxide layer form a gate electrode. Using the gate electrode as a mask, the substrate is implanted with impurities to provide source and drain electrodes. A dielectric layer is formed on polysilicon layer. A contact window (via) is formed in a predetermined area of dielectric layer. An insulator is deposited and defined by etching, on dielectric layer and the contact window. On the insulator and dielectric layer, a metal contact layer is deposited and defined to cover the insulator.