Patents by Inventor Chih-Hung Lin

Chih-Hung Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8546226
    Abstract: A method for fabricating a silicon-oxide-nitride-oxide-silicon (SONOS) non-volatile memory cell, wherein the method comprises steps as following: a pad oxide layer and a first hard mask layer are sequentially formed on a substrate. The pad oxide layer and the first hard mask layer are then etched through to form an opening exposing a portion of the substrate. Subsequently, an oxide-nitride-oxide (ONO) structure with a size substantially less than or equal to the opening is formed to coincide with the portion of the substrate exposed from the opening.
    Type: Grant
    Filed: July 25, 2011
    Date of Patent: October 1, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Ming Wang, Ping-Chia Shih, Chun-Sung Huang, Chi-Cheng Huang, Hsiang-Chen Lee, Chih-Hung Lin, Yau-Kae Sheu
  • Patent number: 8546871
    Abstract: A non-volatile memory cell includes a substrate, two charge trapping structures, a gate oxide layer, a gate and two doping regions. The charge trapping structures are disposed on the substrate separately. The gate oxide layer is disposed on the substrate between the two charge trapping structures. The gate is disposed on the gate oxide layer and the charge trapping structures, wherein the charge trapping structures protrude from two sides of the gate. The doping regions are disposed in the substrate at two sides of the gate.
    Type: Grant
    Filed: July 6, 2011
    Date of Patent: October 1, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Chi-Cheng Huang, Ping-Chia Shih, Chih-Ming Wang, Chun-Sung Huang, Hsiang-Chen Lee, Chih-Hung Lin, Yau-Kae Sheu
  • Publication number: 20130229575
    Abstract: A digital TV data processing method includes: (a) when a first channel digital TV data corresponding to a first channel is displayed, storing a second channel digital TV data corresponding to a second channel, the second channel digital TV data including an audio data and a video data; (b) when the first channel is switched to the second channel, decoding the video data of the stored second channel digital TV data at a first rate; and (c) when the decoding catches up a real-time second channel digital TV data corresponding to the second channel, decoding subsequent second channel digital TV data at a second rate and displaying a corresponding real-time decoding result; wherein the first rate is higher than the second rate.
    Type: Application
    Filed: February 27, 2013
    Publication date: September 5, 2013
    Applicant: MSTAR SEMICONDUCTOR, INC.
    Inventors: Chih-Hung Lin, Kun-chin Han, Yu Fen Tsai
  • Publication number: 20130229143
    Abstract: A multi-party communication control system and charge process of a DC charging system is provided. According battery pack information transmitted by a battery control system, a multi-party communication control device determines a charge current or a charge voltage and a voltage-controlled charge mode required by a battery pack. The multi-party communication control device then translates the charge voltage or the charge current to a CHAdeMO language that is next transmitted to a CHAdeMO charger.
    Type: Application
    Filed: March 10, 2012
    Publication date: September 5, 2013
    Applicant: Ship and Ocean Industries R&D Center
    Inventors: SHEAN-KWANG CHOU, Ying-Chao Liao, Hung-Gsi Lin, Chih-Hung Lin, Sheng-Hua Chen, Hsiao-Yu Hsu, Ming-En Fang, Kai-Ping Hsu, Wen-Hua Pan
  • Patent number: 8490192
    Abstract: A method and a system for cleaning malicious software (malware), a computer program product, and a storage medium are provided. A relation graph is established to associate processes in an operating system and related elements. A node marking action is performed on the relation graph when a predetermined condition is satisfied. The node corresponding to a malicious process and its related nodes are marked with a first label. The nodes of other normal processes and their related nodes are marked with a second label. Then, those nodes marked with both the first label and the second label are screened, so that each of the nodes is marked with only the first label or the second label. Finally, the processes and elements corresponding to the nodes marked with the first label are removed.
    Type: Grant
    Filed: October 1, 2009
    Date of Patent: July 16, 2013
    Assignee: Institute for Information Industry
    Inventors: Shih-Yao Dai, Yu-Chen Chang, Jain-Shing Wu, Chih-Hung Lin, Yen-Nun Huang, Sy-Yen Kuo
  • Patent number: 8477493
    Abstract: A storage device for a tablet personal computer is provided. The storage device includes a base and an upper cover for fixing the tablet personal computer. The base includes a foldable structure. When the foldable structure is folded and stacked on a side of the base, a receiving space for fixing a keyboard device is defined by the base and the foldable structure. In such way, the tablet personal computer and the keyboard device can be simultaneously stored within the storage device.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: July 2, 2013
    Assignee: Primax Electronics, Ltd.
    Inventors: Chun-Che Wu, Chun-Nan Su, Chih-Hung Lin, Chung-Chun Wu
  • Patent number: 8471973
    Abstract: This invention in one aspect relates to a pixel structure. In one embodiment, the pixel structure includes a scan line formed on a substrate and a data line formed over the substrate defining a pixel area, a switch formed inside the pixel area on the substrate, a shielding electrode formed over the switch, a plane organic layer formed over the date line and the pixel area and having no overlapping with the shielding electrode, and a pixel electrode having a first portion and a second portion extending from the first portion, and formed over the shielding electrode and the plane organic layer in the pixel area, wherein the first portion is overlapped with the shielding electrode so as to define a storage capacitor therebetween, and the second portion overlays the plane organic layer and has no overlapping with the data line.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: June 25, 2013
    Assignee: AU Optronics Corporation
    Inventors: Hsiang-Lin Lin, Ching-Huan Lin, Chih-Hung Shih, Wei-Ming Huang, Chih-Hung Lin, Yu-Cheng Chen, Yi-Hui Li, Tsan-Chun Wang
  • Patent number: 8458785
    Abstract: An information security protection host is provided. The information security protection host comprises a network interface and a virtual machine monitor (VMM) device. The network interface is connected to a computer network and is configured to receive a first packet. The VMM device is configured to run a first operating system, wherein the first operating system provides a first network service. The VMM device is further configured to provide a first operating system information of the first operating system and a first network service information of the first network service instantaneously so as to determine the security of the first packet.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: June 4, 2013
    Assignee: Institute for Information Industry
    Inventors: Chih-Hung Lin, Chin-Wei Tien, Sheng-Hao Wang
  • Patent number: 8456582
    Abstract: An active device, a pixel structure, and a display panel are provided. The pixel structure includes a scan line, a data line, an active device, a gate insulating layer, a pixel electrode, a capacitor electrode, and a capacitor dielectric layer. The active device includes a gate, a channel, a source, and a drain. The gate is electrically connected to the scan line. The source is electrically connected to the data line. The gate insulating layer is disposed between the gate and the channel. The pixel electrode is electrically connected to the drain. The capacitor electrode is located on the gate insulating layer. The capacitor dielectric layer is located between the capacitor electrode and the drain.
    Type: Grant
    Filed: February 18, 2011
    Date of Patent: June 4, 2013
    Assignee: Au Optronics Corporation
    Inventors: Yu-Cheng Chen, Yi-Hui Li, Chih-Hung Lin, Maw-Song Chen
  • Publication number: 20130126871
    Abstract: A pixel structure includes a first electrode on a substrate, a first insulation layer covering the first electrode, a gate located on the first insulation layer, a second electrode located on the first insulation layer above the first electrode, a second insulation layer covering the gate and the second electrode, a semiconductor layer located on the second insulation layer above the gate, a source and a drain that are located on the semiconductor layer, a third electrode, a third insulation layer, and a pixel electrode. The third electrode is located on the second insulation layer above the second electrode and electrically connected to the first electrode. The third insulation layer covers the source, the drain, and the third electrode. The pixel electrode is located on the third insulation layer and electrically connected to the drain.
    Type: Application
    Filed: February 23, 2012
    Publication date: May 23, 2013
    Applicant: Au Optronics Corporation
    Inventors: Chuan-Sheng Wei, Chau-Shiang Huang, Wu-Liu Tsai, Chih-Hung Lin, Maw-Song Chen
  • Patent number: 8421938
    Abstract: A pixel array is located on a substrate and includes a plurality of pixel sets. Each of the pixel sets includes a first scan line, a second scan line, a data line, a data signal transmission line, a first pixel unit, and a second pixel unit. The data line is not parallel to the first and the second scan lines. The data signal transmission line is disposed parallel to the first and the second scan lines and electrically connected to the data line. Distance between the first and the second scan lines is smaller than distance between the data signal transmission line and one of the first and the second scan lines. The first pixel unit is electrically connected to the first scan line and the data line. The second pixel unit is electrically connected to the second scan line and the data line.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: April 16, 2013
    Assignee: Au Optronics Corporation
    Inventors: Yi-Hui Li, Yu-Cheng Chen, Tsan-Chun Wang, Chih-Hung Lin, Tung-Huang Chen
  • Publication number: 20130075766
    Abstract: A thin film transistor device, disposed on a substrate, includes a gate electrode, a semiconductor channel layer, a gate insulating layer disposed between the gate electrode and the semiconductor channel layer, a source electrode and a drain electrode disposed at two opposite sides of the semiconductor channel layer and partially overlapping the semiconductor channel layer, respectively, a capacitor electrode at least partially overlapping the gate electrode, and a capacitor dielectric layer disposed between the capacitor electrode and the gate electrode. The capacitor electrode, the gate electrode and the capacitor dielectric layer form a capacitor device.
    Type: Application
    Filed: April 16, 2012
    Publication date: March 28, 2013
    Inventors: Che-Chia Chang, Sheng-Chao Liu, Wu-Liu Tsai, Chuan-Sheng Wei, Chih-Hung Lin
  • Publication number: 20130067470
    Abstract: A virtual machine monitoring method used in a virtual machine monitoring system is provided. The virtual machine monitoring method includes retrieving a hypercall transmitted from one of a plurality of virtual machines to a hypervisor of a virtual machine monitoring system, wherein the hypercall is used for establishing a channel between a source virtual machine and a target virtual machine. A central control virtual machine ID information in the hypervisor is retrieved. A type of the channel established by the hypercall is determined according to the central control virtual machine ID information and channel-establishing information corresponding to the hypercall. When the channel is a private channel that is not related to a central control virtual machine of the virtual machines, a security module is used to monitor the private channel.
    Type: Application
    Filed: November 2, 2011
    Publication date: March 14, 2013
    Applicant: INSTITUTE FOR INFORMATION INDUSTRY
    Inventors: Zhi-Wei Chen, Chia-Wei Tien, Chin-Wei Tien, Chih-Hung Lin
  • Patent number: 8383480
    Abstract: A method for forming a semiconductor structure includes following steps. A substrate structure is provided. The substrate structure includes a semiconductor substrate, a first oxide-nitride-oxide (ONO) layer, and a second ONO layer. The semiconductor substrate has first and second surfaces opposite to each other. The first ONO layer includes a first oxide layer, a first nitride layer and a second oxide layer formed on the first surface in sequence. The second ONO layer includes a third oxide layer, a second nitride layer and a fourth oxide layer formed on the second surface in sequence. A nitride mask layer is formed on the first ONO layer. The fourth oxide layer is removed. The second nitride layer and the nitride mask layer are removed. The second oxide layer and the third oxide layer are removed. A fifth oxide layer is formed on the first nitride layer.
    Type: Grant
    Filed: November 14, 2011
    Date of Patent: February 26, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Ming Wang, Ping-Chia Shih, Chi-Cheng Huang, Hsiang-Chen Lee, Chih-Hung Lin
  • Publication number: 20130026557
    Abstract: A method for fabricating a silicon-oxide-nitride-oxide-silicon (SONOS) non-volatile memory cell, wherein the method comprises steps as following: a pad oxide layer and a first hard mask layer are sequentially formed on a substrate. The pad oxide layer and the first hard mask layer are then etched through to form an opening exposing a portion of the substrate. Subsequently, an oxide-nitride-oxide (ONO) structure with a size substantially less than or equal to the opening is formed to coincide with the portion of the substrate exposed from the opening.
    Type: Application
    Filed: July 25, 2011
    Publication date: January 31, 2013
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Ming WANG, Ping-Chia SHIH, Chun-Sung HUANG, Chi-Cheng HUANG, Hsiang-Chen LEE, Chih-Hung LIN, Yau-Kae SHEU
  • Publication number: 20130021543
    Abstract: A photosensitive resin composition includes: a copolymer obtained by subjecting a conjugated diene polymer having a (meth)acryloyl group, a conjugated diene monomer, and a (meth)acrylic acid monomer to copolymerization; a compound having at least one ethylenically unsaturated group; and a photoinitiator. The copolymer contains 60 wt % to 99 wt % of a copolymer fraction having a molecular weight ranging from 30,000 to 900,000, and 1 wt % to 22 wt % of a copolymer fraction having a molecular weight ranging from 1,000 to 10,000 when calculated from an integral molecular weight distribution curve obtained by plotting cumulative weight percentage versus molecular weight falling within a range between 1,000 and 1,000,000 measured by gel permeation chromatography.
    Type: Application
    Filed: July 11, 2012
    Publication date: January 24, 2013
    Applicant: CHI MEI CORPORATION
    Inventors: Chih-Hung LIN, Chia-Hui YU
  • Publication number: 20130012669
    Abstract: A thermosetting resin composition includes an epoxy resin, a polyetheramine curing agent, and an epoxy silane coupling agent. The polyetheramine curing agent is in an amount less than or equal to 10 parts by weight and the epoxy silane coupling agent is in an amount more than or equal to 10 parts by weight based on 100 parts by weight of the epoxy resin.
    Type: Application
    Filed: June 21, 2012
    Publication date: January 10, 2013
    Inventors: Chih-Hung LIN, Chia-Hui Yu
  • Publication number: 20130009232
    Abstract: A non-volatile memory cell includes a substrate, two charge trapping structures, a gate oxide layer, a gate and two doping regions. The charge trapping structures are disposed on the substrate separately. The gate oxide layer is disposed on the substrate between the two charge trapping structures. The gate is disposed on the gate oxide layer and the charge trapping structures, wherein the charge trapping structures protrude from two sides of the gate. The doping regions are disposed in the substrate at two sides of the gate.
    Type: Application
    Filed: July 6, 2011
    Publication date: January 10, 2013
    Inventors: Chi-Cheng Huang, Ping-Chia Shih, Chih-Ming Wang, Chun-Sung Huang, Hsiang-Chen Lee, Chih-Hung Lin, Yau-Kae Sheu
  • Publication number: 20120293953
    Abstract: A storage device for a tablet personal computer is provided. The storage device includes a base and an upper cover for fixing the tablet personal computer. The base includes a foldable structure. When the foldable structure is folded and stacked on a side of the base, a receiving space for fixing a keyboard device is defined by the base and the foldable structure. In such way, the tablet personal computer and the keyboard device can be simultaneously stored within the storage device.
    Type: Application
    Filed: July 28, 2011
    Publication date: November 22, 2012
    Applicant: Primax Electronics Ltd.
    Inventors: Chun-Che Wu, Chun-Nan Su, Chih-Hung Lin, Chung-Chun Wu
  • Patent number: 8286258
    Abstract: A monitor method and a monitor apparatus for monitoring a data of hardware are provided. The data has private information, identification information and at least one first network transmission address. The monitor apparatus comprises a storage unit and a processing unit. The data is stored in the storage unit according to the identification information. The processing unit is configured to record the identification information and the at least one first network transmission address of the data in a mark information table. In response to a sending system call, when a transmission is arranged to transmit the private information of the data to a second network transmission address which is different from the at least one first network transmission address, the processing unit will output a signal to cease the transmission.
    Type: Grant
    Filed: December 4, 2009
    Date of Patent: October 9, 2012
    Assignee: Institute for Information Industry
    Inventors: Chin-Wei Tien, Yao-Ting Chung, Chih-Hung Lin, Jain-Shing Wu