Abstract: A light-emitting device and method for fabricating the same are revealed. The light-emitting device includes an epitaxial structure, a P-type ohmic contact electrode and an N-type ohmic contact electrode. The epitaxial structure includes a plurality of epitaxial layers capable of emitting light and P-type contact layer. The P-type ohmic contact electrode includes a first nickel layer deposited on the epitaxial structure, a first platinum layer deposited on the first nickel layer, and a first gold layer deposited on the first platinum layer. According to the fabricating method of the light-emitting device, an epitaxial structure is first formed on the surface of a substrate, a P-type ohmic contact electrode is then formed on the epitaxial structure, and an N-type ohmic contact electrode is formed on the other surface of the substrate. Finally, an annealing process is performed at a temperature between 220° C. and 330° C.

Abstract: A yield analysis method. First, a wafer having multiple dies is inspected to obtain wafer defect data containing defect information for every die in the wafer. Then a wafer map and an overall yield are generated according to the wafer defect data. The wafer map displays defective dies and defect-free dies in the wafer. Then, first and second systematic limited yields are calculated in accordance with the wafer defect data and the wafer map, wherein the first systematic limited yield is calculated excluding defective dies with localized distribution, and the second systematic limited yield is calculated excluding defective dies with repeated distribution. Then a random defect limited yield is determined in accordance with the overall yield, the first systematic limited yield, and the second systematic limited yield.

Abstract: A programmable level shifter. The programmable level shifter comprises a first P-type FET, a first N-type FET, a second P-type FET, a second N-type FET, an inverter, and a programmable device. The first P-type FET is coupled between a fist power line and an output node. The first N-type FET is coupled between the first P-type FET and a second power line. The programmable device is coupled between the first power line and the output node, which can be programmed to change an effective resistance between the first power line and the output node when the second P-type FET is turned on.

Abstract: A programmable level shifter. The programmable level shifter comprises a first P-type FET, a second P-type FET, a third P-type FET, a fourth P-type FET, a fifth P-type FET, a sixth P-type FET, a first N-type FET, a second N-type FET, a third N-type FET, and a programmable device. The first P-type FET is coupled between a first power line and an output node. The first N-type FET is coupled between the first P-type FET and a second power line. The programmable device is coupled between the first power line and the output node, which can be programmed to change an effective resistance between the first power line and the output node when the second P-type FET is turned on.

Abstract: A programmable level shifter. The programmable level shifter comprises a first P-type FET, a first N-type FET, a second P-type FET, a second N-type FET, an inverter, and a programmable device. The first P-type FET is coupled between a fist power line and an output node. The first N-type FET is coupled between the first P-type FET and a second power line. The programmable device is coupled between the first power line and the output node, which can be programmed to change an effective resistance between the first power line and the output node when the second P-type FET is turned on.

Abstract: A programmable level shifter. The programmable level shifter comprises a first P-type FET, a first N-type FET, a second P-type FET, a second N-type FET, and a programmable device. The first P-type FET is coupled between a fist power line and a non-inverted output node, and a gate pole thereof is coupled to a inverted output node. The first N-type FET is coupled between the first P-type FET and a second power line. The programmable device is coupled between the first power line and the non-inverted output node, which can be programmed to change an effective resistance between the first power line and the inverted output node when the second P-type FET is turned on.

Abstract: A programmable level shifter. The programmable level shifter comprises a first P-type FET, a second P-type FET, a third P-type FET, a fourth P-type FET, a fifth P-type FET, a sixth P-type FET, a first N-type FET, a second N-type FET, a third N-type FET, and a programmable device. The first P-type FET is coupled between a first power line and an output node. The first N-type FET is coupled between the first P-type FET and a second power line. The programmable device is coupled between the first power line and the output node, which can be programmed to change an effective resistance between the first power line and the output node when the second P-type FET is turned on.

Abstract: The present invention disclosed a method and apparatus for removing a SiC or a low k dielectric film, wherein the SiC or low k dielectric film is deposited on a substrate. The method comprising: Process the low k dielectric film or SiC film with high temperature oxidation, such as wet oxidation or dry oxidation, to transform the film into an oxide film layer, then remove the oxide film layer by wet etching. The present invention also disclosed an apparatus to perform the process, comprising: a high temperature processing unit such as a high temperature furnace, and a wet etching unit such as a wet bench or a single wafer spin etching processor. These units may form as a single apparatus, a cluster tool or separate tools.

Abstract: A computer-implemented method and system for identifying process steps for purposes of queue-time control and abnormality detection is provided. In one example, the method includes retrieving manufacturing information associated with a fabrication process, where the manufacturing information includes multiple process step pairs. The manufacturing information may be divided into at least a high group and a low group using a statistical clustering method. Values, such as P-values, may then be calculated for each process step pair by applying a non-parametric statistical method to the high and low groups. The process step pairs may be ranked based on their calculated values, and redundant process step pairs may be eliminated. The remaining process step pairs may then be analyzed to identify a particular process step or process step pair.

Abstract: The present invention is related to a structure of an imprint mold and a method for fabricating the same, which can be used in the field of nano-imprint lithography. Firstly, a diamond film and a photoresist film are successively formed onto a substrate; wherein the photoresist film is more capable of anticorrosion than the diamond film. Then an energy beam lithography system is provided to make the photoresist film form a photoresist mask with particularly arranged patterns. Because of the etching selectivity between the diamond film and the photoresist film, on the surface of the diamond film can be easily formed a pattern with recessions and protrusions according to the photoresist mask by dry etching method. Thus an imprint mold characterized as better antifriction and easily taking off from imprinted materials is completed.

Abstract: A method of forming a CMOS thin film transistor device. A dry etching procedure is performed to remove part of a photoresist layer and part of a metal layer and thus forms a gate with a symmetrical cone shape and a remaining photoresist layer. The dielectric layer is thus exposed in the lightly doped area. Specially, the bottom width of the first gate is narrower than that of the first metal layer and the symmetrical cone shape is gradually thinner from bottom to top. Using the gate as a mask, an n?-ion implantation is performed to form a self-aligned and symmetrical LDD region in a semiconductor layer without additional photolithography steps.

Abstract: A read only memory device includes multiple word lines, a first and second main bit line GL (n) and BL (n), sub-bit lines SB1 (n) to SB4 (n), selection switches MB1 (n) to MB4 (n), and memory cells M1 (n) to M4 (n). The memory cells M1 (n) to M4 (n) are electrically coupled to the sub-bit lines SB1 (n) to SB4 (n) and the sub-bit line SB1 (n+1), respectively. When the memory cell M3 (n) which is connected to SB3 (n) is read, the sub-bit lines SB1 (n) to SB3 (n) are connected to the corresponding main bit lines through the turned selection switches. At this time, the sub-bit lines SB1 (n) to SB3 (n) are not floating but are all at the same high voltage level. Therefore, the capacitance effect will not exist between them to change the voltage level of the sub-bit lines quickly.

Abstract: A light-emitting device and method for fabricating the same are revealed. The light-emitting device includes an epitaxial structure, a P-type ohmic contact electrode and an N-type ohmic contact electrode. The epitaxial structure includes a plurality of epitaxial layers capable of emitting light and P-type contact layer. The P-type ohmic contact electrode includes a first nickel layer deposited on the epitaxial structure, a first platinum layer deposited on the first nickel layer, and a first gold layer deposited on the first platinum layer. According to the fabricating method of the light-emitting device, an epitaxial structure is first formed on the surface of a substrate, a P-type ohmic contact electrode is then formed on the epitaxial structure, and an N-type ohmic contact electrode is formed on the other surface of the substrate. Finally, an annealing process is performed at a temperature between 220° C. and 330° C.

Abstract: A method of forming a CMOS thin film transistor device. A dry etching procedure is performed to remove part of a photoresist layer and part of a metal layer and thus forms a gate with a symmetrical cone shape and a remaining photoresist layer. The dielectric layer is thus exposed in the lightly doped area. Specially, the bottom width of the first gate is narrower than that of the first metal layer and the symmetrical cone shape is gradually thinner from bottom to top. Using the gate as a mask, an n−-ion implantation is performed to form a self-aligned and symmetrical LDD region in a semiconductor layer without additional photolithography steps.

Abstract: A circuit board includes a power switch operable so as to generate a trigger signal upon actuation, a card slot adapted for connecting with a video card, and a controller coupled electrically to the power switch and the card slot. The controller detects connection of the video card to the card slot and further detects operating voltage of the video card. The controller inhibits the power switch from generating the trigger signal upon detection that the operating voltage of the video card that is connected to the card slot is higher than a predetermined voltage.

Abstract: A read only memory device is made up of multiple word lines that are positioned in parallel to each other. The read only memory device includes an nth section, which includes a first main bit line GL (n) and a second main bit line BL (n); a first, a second, a third, and a fourth sub-bit lines SB1 (n) to SB4 (n); and a first, a second, a third, and a fourth selection switches MB1 (n) to MB4 (n), all of which are electrically coupled to the second bit line. The other terminal of the first selection switch MB1 (n) is electrically coupled to the first sub-bit line SB1 (n). The other terminals of each of the second and third selection switches MB2 (n) to MB3 (n) are electrically coupled to the third sub-bit line SB3 (n). The other terminal of the fourth selection switch MB4 (n) is electrically coupled to the first sub-bit line SB1 (n+1) of the (n+1)th section. The second and fourth sub-bit lines SB (2) and SB (4) are electrically coupled to the first main bit line GL (n).

Abstract: A circuit board includes a power switch operable so as to generate a trigger signal upon actuation, a card slot adapted for connecting with a video card, and a controller coupled electrically to the power switch and the card slot. The controller detects connection of the video card to the card slot and further detects operating voltage of the video card. The controller inhibits the power switch from generating the trigger signal upon detection that the operating voltage of the video card that is connected to the card slot is higher than a predetermined voltage.